LTC4162EUFD-FST#PBF datasheet(29/52 Pages) AD

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LTC4162-F

Rev A

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SMBus and I2C Protocol Compatibility

The LTC4162 uses an SMBus/I2C style 2-wire serial port

for some programming and all monitoring functions. Over

the serial port the user may program alert values which

are compared against measured parameters, set control

parameters and read status data. The Timing Diagram

shows the relationship of the signals on the bus. The two

bus lines, SDA and SCL, must be high when the bus is not

inuse.Externalpull-upresistorsarerequiredontheselines.

TheLTC4162isbothaslavereceiverandslavetransmitter.

It is never a master. The control signals, SDA and SCL,

are scaled internally to the DVCC supply for compliance

with the I2C specification. DVCC should be connected to

the same power supply as the bus pull-up resistors.

Asidefromelectricallevelsandbusspeed,theSMBusspec-

ification is generally compatible with the I2C specification,

but extends beyond I2C to define and standardize specific

formats for various types of transactions. The LTC4162

serial port is compatible with the 0Hz-400kHz speed and

ratiometric input thresholds of the I2C specification, but

supports both the Read-Word and Write-Word protocols

of the SMBus specification, either with or without packet

error checking (PEC). The SMBALERT and ARA protocols

of the SMBus specification are also supported. Finally, it

has built-in timing delays and glitch suppression filters to

ensure correct operation with both protocols.

The input logic levels of I2C and SMBus are specified dif-

ferently. I2C specifies logic levels that are ratiometric to

supplyandSMBusspecifiesabsolutelevels.Bycomparing

the specifications, it can be shown that the logic levels

are compatible for supply voltages ranging from 2.667V

to 3.000V, however, with a well designed system, I2C

compatible and SMBus compatible parts are often found

to be interchangeable. Appendix B of System Manage-

ment Bus (SMBus) Specification Version 2.0 highlights

differences between SMBus and I2C, as does section 4 of

I2C-bus Specification and User Manual.

APPLICATIONS INFORMATION

Alternate Thermistors and Biasing

Thermistors with a βvaluehigherthan3490Kmaybeused

with the LTC4162 by either diluting the thermistor with

an inexpensive low drift series resistor, RSERIES, or over-

writing jeita_t1 through jeita_t6 with appropriate values.

If a single dilution resistor is added, RNTCBIAS should be

increased by an amount equal to the dilution resistor to

pad the bias resistor, thereby returning the resistor ratio

to 50% and, therefore, yielding no error at 25°C. Slightly

more padding of RNTCBIASmaybedesiredtoliftandcenter

the error curve over a given temperature range. With the

addition of one more resistor, RPARALLEL,tothethermistor

biasnetwork,it'spossibletofurtherrefinethetemperature

profile of a higher β thermistor to match the expected β

value of 3490K. The values of RNTCBIAS, RPARALLEL and

RSERIES can be selected to nearly match the thermistor

profile expected by the LTC4162. An example is included

here as a demonstration.

4162F F03

RSERIES

RNTCBIAS

RPARALLEL

RNTC

NTC

THERMISTOR

NTCBIAS

Figure 3. Diluting the Thermistor with Low Drift Series and

Parallel Resistors

For a 10k Vishay NTCS0402E3103FHT thermistor which

has a β25/75 value of 3950K, using RNTCBIAS = 10k, RSER-

IES = 549 and RPARALLEL = 187k will closely mimic the

profile of a thermistor β value of 3490K over the 0°C to

60°C range resulting in a nominal error of under ±0.5°C

for the default JEITA temperature thresholds defined by

jeita_t1 through jeita_t6. This error is significantly less

than the error tolerance of most thermistors.

LTC4162EUFD-FST#PBF Datasheet(PDF) 29 Page - Analog Devices

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