LTC4162EUFD-FST#PBF datasheet(33/52 Pages) AD

33 / 52 page

LTC4162-F

Rev A

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APPLICATIONS INFORMATION

time. If possible, the BATSENS+ pin should be connected

to the battery terminals with a separate Kelvin connection

from that of the current carrying inductor path. The bulk

load capacitor should be on the inductor side of this

connection, not the BATSENS+ side. A smaller ceramic

capacitor may additionally be added to the BATSENS+

pin near the LTC4162. A heavy copper run from the low

side of battery to the GND (paddle) of the LTC4162 is also

necessary to reduce resistance optimizing charging time.

Resistive Inputs and Test Equipment

Care must be exercised in the laboratory while evaluat-

ing the LTC4162 with inline ammeters. The combined

resistance of the internal current sense resistor and fuse

of many meters can be 0.5Ω or more. At currents of 3A+

it is possible to drop several volts across the meter and

wiring, possibly resulting in unusual voltage readings or

artificially high switch duty cycles. A resistive connection

to the source of input power can be particularly trouble-

some. With the undervoltage limit feature enabled, the

switching regulator output power will be automatically

reduced to prevent VIN from falling below its programmed

level. This feature greatly improves tolerance to resistive

input power sources (from either undersized wiring and

connectors or test equipment) and facilitates stable be-

havior, but if engaged, could result in much less power

delivery to the battery.

Solar Panel Input Impedance Correction

The maximum power point tracking algorithm uses the

LTC4162's input voltage regulation control loop to find

and operate at the maximum power point of the solar

panel. In general solar panels have two distinct regions of

operation roughly corresponding to constant voltage and

constant current. In its constant voltage region the panel

presents a somewhat low impedance and in its constant

current region a very high impedance. Figure 7 shows an

I-V characteristic collected from a brightly lit high quality

40W solar panel. Notice the very high impedance below

16V and fairly low impedance above 16V.

PANEL VOLTAGE (V)

0.0

0.4

0.8

1.2

1.6

2.0

4162F F07

CONSTANT CURRENT

CONSTANT VOLTAGE

Figure 7. High Quality 40W Solar Panel

When the driving impedance is at or below a few Ohms

the LTC4162's input voltage regulation loop is very stable.

However, in its attempt to find the maximum power point,

the LTC4162 drags the panel voltage down to its constant-

currenthighimpedanceregion.InthisregiontheLTC4162

input voltage control loop will become unstable. To avoid

instability and UVLO restarts the real input impedance of

the LTC4162 should be maintained at about 2.5Ω in the

1kHz to 10kHz band. To achieve this characteristic an R-C

network should be added to the solar panel. For example,

a lower quality 100μF to 1000μF capacitor plus a 2.5Ω

series resistor would make a good impedance correction

network as shown in Figure 8.

0.1µF

–

INFET CLP

VIN

2.5

CLN

LTC4162

4162F F08

150µF

Figure 8. Input Impedance Compensation Network

Figure 9 shows the driving impedance presented by the

combined solar panel plus 10μF bypass capacitor on VOUT

in both low impedance and high impedance solar panel

regions.Inthelowimpedanceregiontheaggregateimped-

ance characteristic is about one to three Ohms in parallel

LTC4162EUFD-FST#PBF Datasheet(PDF) 33 Page - Analog Devices

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