LTC4162EUFD-FST#PBF datasheet(11/52 Pages) AD

11 / 52 page

LTC4162-F

Rev A

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PIN FUNCTIONS

NTC (Pin 10): Thermistor input. The NTC pin connects to

a negative temperature coefficient thermistor to monitor

the temperature of the battery. The voltage on this pin

is digitized by the analog to digital converter to qualify

battery charging and is available for readout via the I2C

port. A low drift bias resistor is required from NTCBIAS

to NTC and a thermistor is required from NTC to ground.

RT (Pin 11): Switching regulator frequency control pin.

The RT pin controls the switching regulator's internal

oscillator frequency by placing a resistor from RT to GND.

SMBALERT (Pin 12): Interrupt output. This open drain

output pulls low when one or more of the programmable

alerts is triggered.

SCL (Pin 13): Open drain clock input for the I2C port. The

I2C port input levels are scaled with respect to DVCC for

I2C compliance.

SDA (Pin 14): Open drain data input/output for the I2C

port. The I2C port input levels are scaled with respect to

DVCC for I2C compliance.

DVCC (Pin 15): Logic supply for the I2C port. DVCC sets the

reference level of the SDA and SCL pins for I2C compli-

ance. It should be connected to the same power supply

as the SDA and SCL pull up resistors.

SYNC(Pin16):Optionalexternalclockinputfortheswitch-

ing battery charger. The switching battery charger will

lock to a square wave or pulse on this pin that is close to

the frequency programmed by the RT pin. Ground SYNC

if this feature is not needed.

CELLS0 (Pin 17): Cell count selection pin. Used in com-

bination with CELLS1, this pin sets the total number of

series cells to be charged. The pin should be strapped to

either INTVCC, VCC2P5 or GND to represent one of three

possible states. See Table 5.

CELLS1 (Pin 18): Cell count selection pin. Used in com-

bination with CELLS0, this pin sets the total number of

series cells to be charged. The pin should be strapped to

either INTVCC, VCC2P5 or GND to represent one of three

possible states. See Table 5.

BATSENS+ (Pin 19): Positive terminal battery sense pin.

BATSENS+shouldKelvinsensethepositiveterminalofthe

battery for optimized charging. A 10µF multilayer ceramic

capacitor is required from BATSENS+ to ground.

CSN (Pin 20): Connection point for the negative terminal

of the current sense resistor used to measure and limit

charge current.

CSP (Pin 21): Connection point for the positive terminal

of the current sense resistor used to measure and limit

charge current.

BATFET (Pin 22): Gate control pin for a reverse blocking

externalN-channelMOSFETbetweenthebatteryandVOUT.

PGND(Pins23,24):Powergroundpins.Thesepinsshould

be connected to a copper pour that forms the return for

the VOUT bypass capacitor on the top layer of the printed

circuit board.

SW (Pin 25, 26): Switching regulator power transmission

pins. The SW pins deliver power from the VOUT pins to the

battery via the step-down switching regulator. An inductor

should be connected from SW to a sense resistor at CSP.

See the Applications Information section for a discussion

of inductor value and current rating.

VOUT (Pin 27, 28): Switching regulator input pins. The

VOUT pins deliver power to the switching charger. Having

extremely high frequency current pulses, bypassing of

the VOUT pins should take precedence over all other PCB

layout considerations. A bypass capacitor of 10µF is a

good starting point.

AGND (Exposed PAD, Pin 29): Analog ground pin. This

is the ground pin used to return all of the analog circuitry

inside the LTC4162 and should be connected to an analog

ground pour that is common with PGND (pins 23 and 24).

It should also be connected to a ground plane on layer 2

of the PCB to which all of the analog components return

such as the RT resistor and the INTVCC and VCC2P5 by-

pass capacitors.

LTC4162EUFD-FST#PBF Datasheet(PDF) 11 Page - Analog Devices

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