LTC4162EUFD-FST#PBF datasheet(35/52 Pages) AD

35 / 52 page

LTC4162-F

Rev A

For more information www.analog.com

APPLICATIONS INFORMATION

minimize parasitic inductance, the ground plane should

be as close as possible to the top plane of the PC board

(i.e. layer 2).

4162F F10

Figure 10. Currents Tend to Follow Their Natural Least

Area Path. Breaks in the Ground Plane Lead to Increased

Impedance and EMI

The capacitor from VOUT to PGND is the most critical high

frequencycomponent.It'sproximitytotheLTC4162should

be prioritized above all else. The LTC4162 is designed to

have this capacitor placed directly adjacent to the short

side of the package where the connections to pins (27,28)

and (23,24) can be made on the top copper layer of the

PC board (see Figures 12 and 13). The inductor connec-

tion to SW should feed out between the input capacitor

terminals or down to a lower layer with a group of vias

very close to the LTC4162.

+–

VIN

HOT LOOP

COUT

4162F F11

CBAT

VBAT

Figure 11. Hot Loop

4162F F12

Figure 12. Recommended Placement of the VOUT Bypass

Capacitor and Inductor

Figure 13. Recommended Placement of the VOUT Bypass

Capacitor and Inductor

Due to its high frequency switching circuitry, it is also

imperative that the INTVCC and VCC2P5 LDO capacitors

as well as the BOOST-SW capacitor be as close to the

LTC4162 as possible. Additionally, minimizing the SW

pin trace area will help minimize high frequency radiated

energy.

The ceramic capacitor on BATSENS+ carries the inductor

ripple current. While not as critical as the VOUT bypass

capacitor, an unbroken copper pour from this capacitor's

lowsidetotheLTC4162PGNDpins(23,24)andtheanalog

ground pin (paddle) will reduce output voltage ripple and

ensure proper regulation.

The LTC4162 demonstration board DC2038A provides an

excellent example of a suitable PC board layout.

LTC4162EUFD-FST#PBF Datasheet(PDF) 35 Page - Analog Devices

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