ADP5360ACBZ-2-R7 datasheet(32/60 Pages) AD

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ADP5360

Data Sheet

Rev. 0 | Page 32 of 60

Manual Reset Input

The ADP5360 features a manual reset input. When driving the

MR pin low from high with the deglitch time (tDG), the INT pin

asserts an interrupt when the EN_MR_INT bit, Address 0x33, is

set to high. When the MR pin transitions from low to high, the

RESET pin output asserts and remains asserted for the duration

of the reset timeout period (tRP) before deasserting. Connect an

external pull-up resistor from tthe MR input to the VDD pin for

a logic high output. To generate a reset, connect an external push-

button switch between the MR pin and ground. Noise immunity

is provided on the MR input, and fast transients going in a negative

direction are ignored. A 0.1 μF capacitor between the MR pin and

ground provides additional noise immunity if required.

VOUT1

RESET

tRP

MR EXTERNAL LY

DRIVEN LOW

tRP

INT

tDG

Figure 55. Manual Reset Timing Diagram

When the EN_MR_SD bit, Address 0x2D is set to enable

shipment mode, pulling down the MR pin for more than a

12 second time out,and then releasing the MR pin, shuts down

all function blocks, and the ADP5360 then enters shipment

mode. To exit shipment mode, pull the MR pin low for tSH, and

the ADP5360 restarts with the default factory setting registers.

Watchdog Timer

The ADP5360 features a watchdog timer that monitors

microprocessor activity. A timer circuit is cleared with every

write to the RESET_WD bit, Address 0x2D. If the timer counts

through the preset watchdog timeout period (tWD), a RESET

output asserts. The microprocessor must toggle the

RESET_WD bit to avoid being reset.

When RESET is asserted, the watchdog timer clears and does

not count again until the RESET output deasserts. To disable

the watchdog timer, set the EN_WD bit, Address 0x2D via the

I2C interface. Note that the watchdog timer is ignored when

RESET is not activated.

If the watchdog timer expires without being reset while in

charger mode, the ADP5360 charger assumes there is a software

problem and triggers tSAFE. For more information, see the Safety

Timer section.

SHIPMENT MODE

The ADP5360 provides optional shipment mode as a default

status after ISOB powers up. During shipment mode, most

function blocks shut down, including the ISOFET and VSYS

output voltages that realize an ultralow shutdown current. In

addition, during shipment mode, the PGOOD1, PGOOD2, and

RESET pins have a high output by default.

Enable shipment mode at initial power up of the ADP5360 by

pulling up the ENSD pin. To disable shipment mode, pull down

the ENSD pin.

In the case where the VBUS voltage goes higher than the UVLO

or the MR pin for tSH is pulled down, the ADP5360 exits shipment

mode. To re-enter shipment mode, set the EN_SHIPMODE bit,

Address 0x36, to high or pull down the MR pin for 12 seconds.

Note that the EN_MR_SD bit, Address 0x2D must be set to

enable the MR shipment function.

FAULT RECOVERY

Before performing fault recovery, ensure that the cause of the

fault is rectified.

To recover from a fault status, power off the VBUS pin or write

a high to the corresponding bits of the Fault register.

THERMAL MANAGEMENT

Thermal Shutdown

The ADP5360 features a shutdown threshold detector. If the die

temperature exceeds TSD, all functions are disabled, and the

TSD110 bit, Address 0x2E, is set. The ADP5360 charger can be

re-enabled when the die temperature drops lower than the TSD

falling limit, and the TSD110 bit is reset. To reset the TSD110

bit, write to the I2C fault register, THERMISTOR_10C

Threshold, Address 0x0D, or cycle the power.

ADP5360ACBZ-2-R7 Datasheet(PDF) 32 Page - Analog Devices

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