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ADP5360ACBZ-2-R7 Datasheet(PDF) 10 Page - Analog Devices |
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ADP5360ACBZ-2-R7 Datasheet(HTML) 10 Page - Analog Devices |
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10 / 60 page ![]() ADP5360 Data Sheet Rev. 0 | Page 10 of 60 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS STP SDA INT ENSD EN2 PGND1 PGOOD1 ENCHG SCL THR ILIM PGOOD2 VDD ISOB MR A B C D E 1 234 VOUT2 FB1 SW1 SW2B 5 PGND2 VIN2 SW2A VIN1 AGND1 RESET VSYS F 6 BSNS AGND2 VID1 EN1 ICS VBUS Figure 3. Ball Configuration (Top View) Table 9. Ball Function Descriptions Ball No. Mnemonic Description A1 PGND2 Power Ground for the Buck Boost Regulator. A2 SW2B Switching Node for the Buck Boost Regulator. A3 VOUT2 Buck Boost Regulator Output Pin. A4 SCL I2C Serial Clock. This pin requires an external pull-up resistor. A5 SDA I2C Serial Data. This pin requires an external pull-up resistor. A6 INT Processor Interrupt (Active Low). This pin requires an external pull-up resistor. If this pin is not used, this pin can be left floating. B1 SW2A Switching Node for the Buck Boost Regulator. B2 AGND2 Analog Ground. B3 ENSD Shutdown Mode Select. When this pin is low, the shutdown mode disables. When this pin is high, the shutdown mode enables. B4 EN2 Enable Pin for Buck Boost Regulator. B5 PGOOD1 Power-Good Signal Output. This open-drain output is the power-good signal for the selected VBUSOK, BATOK, CHG_CMPLT, VOUT2OK, or VOUT1OK bits (see Table 65). B6 THR Battery Pack Thermistor Connection. C1 VIN2 Input Power for the Buck Regulator. C2 STP Stop Switching for the Selected Channel. C5 PGOOD2 Power-Good Signal Output. This open-drain output is the power-good signal for the selected VBUSOK, BATOK, CHG_CMPLT, VOUT2OK, or VOUT1OK bits (see Table 65). C6 BSNS Battery Voltage Sense. D1 FB1 Feedback Sensing Input for the Buck Regulator. D2 VID1 Configure Buck Regulator Output Voltage. Connect a resistor from VID1 to AGND1 and AGND2 to program the buck regulator default output voltage. Float the pin to disable the pin select feature and use the register default set. D5 ILIM Input Current-Limit Select. Connect a resistor to AGND1 and AGND2 to set the default input current-limit level. Float the pin to disable the pin select feature and use the register default set. D6 ISOB Battery Supply-Side Input to Internal Isolation FET. |
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