ADP5360ACBZ-2-R7 datasheet(33/60 Pages) AD

33 / 60 page

Data Sheet

ADP5360

Rev. 0 | Page 33 of 60

I2C INTERFACE

The ADP5360 includes an I2C-compatible serial interface to

control the battery charging, fuel gauge, buck, and buck boost,

and to read back the system status.

I2C ADDRESSES

The I2C chip default address is 0x46. Different I2C addresses can

be factory programmable. Having different I2C address options

helps to avoid I2C address conflicts with other I2C slave chipsets

in the system. For different I2C chip address requirements,

contact the local Analog Devices sales or distribution

representative.

SDA AND SCL PINS

The ADP5360 has two dedicated I2C interface pins, SDA and SCL.

SDA is an open-drain line for receiving and transmitting data. SCL

is an input line for receiving the clock signal. Pull up these pins to

connect external input and output supplies using external

resistors.

Serial data is transferred on the rising edge of SCL. The read

data is generated at the SDA pin in read mode.

The subaddress content selects which of the ADP5360 registers

is written to first. The ADP5360 sends an acknowledgement to

the master after the 8-bit data byte is written (see Figure 56 for an

example of the I2C write sequence to a single register). The

ADP5360 increments the subaddress automatically and starts

receiving a data byte at the next register until the master sends

an I2C stop as shown in Figure 56.

INTERRUPTS

The ADP5360 provides an interrupt output (INT pin) for an

interrupt case. During normal operation, the INT pin is pulled

high using an external pull-up resistor. When an interrupt case

occurs, the ADP5360 pulls the INT pin low to alert the I2C host

that an interrupt case has occurred.

Many different interrupt sources can trigger the INT pin. By

default, no interrupt sources are configured. To select one or more

interrupt sources to trigger the INT pin, set the corresponding bits

to 1 in the INTERRUPT_ENABLE1 and INTERRUPT_ENABLE2

registers.

When the INT pin is triggered, the corresponding bits in the

INTERRUPT_FLAG1 and INTERRUPT_FLAG2 registers are

set to 1. The interrupt case that triggers the INT pin is read

from the INTERRUPT_FLAG1 and INTERRUPT_FLAG2

registers.

To clear an interrupt, write a 1 to the corresponding bit in the

INTERRUPT_FLAG1 and INTERRUPT_FLAG2 registers.

Otherwise, the ADP5360 power recycles. Reading the interrupt

or writing a 0 to the bit does not clear the interrupt.

SUBADDRESS

CHIP ADDRESS

010

0 SP

ADP5360 RECEIVES

DATA

0 = WRITE

MASTER STOP

Figure 56. I2C Single Register Write Sequence

CHIP ADDRESS

SUBADDRESS

ADP5360 RECEIVES

DATA TO REGISTER N

ADP5360 RECEIVES

DATA TO REGISTER N + 1

ADP5360 RECEIVES

DATA TO LAST REGISTER

010

0 = WRITE

MASTER STOP

Figure 57. I2C Multiple Register Write Sequence

ADP5360ACBZ-2-R7 Datasheet(PDF) 33 Page - Analog Devices

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