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ADP5360ACBZ-2-R7 Datasheet(PDF) 53 Page - Analog Devices

Part # ADP5360ACBZ-2-R7
Description  Advanced Battery Management PMIC with Ultra Low Power Buck and Buck Boost
PDF  60 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADP5360ACBZ-2-R7 Datasheet(HTML) 53 Page - Analog Devices

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Data Sheet
ADP5360
Rev. 0 | Page 53 of 60
Table 70. INTERRUPT_FLAG1 Register, Address 0x34 Bit Descriptions
Bit(s) Bit Name
Access Default
Description
7
SOCLOW_INT1
R
Not applicable
When high, this bit indicates an interrupt caused by low battery voltage.
6
SOCACM_INT1
R
Not applicable
When high, this bit indicates an interrupt caused by state of charge accumulation to
4096 points and an overflow of points.
5
ADPICHG_INT
R
Not applicable
When high, this bit indicates an interrupt caused by VBUS input current-limit
adaptive regulation.
4
BATPRO_INT1
R
Not applicable
When high, this bit indicates an interrupt caused by battery protection triggered with
battery fault events.
3
THR_INT1
R
Not applicable
When high, this bit indicates an interrupt caused by THR temperature thresholds.
2
BAT_INT1
R
Not applicable
When high, this bit indicates an interrupt caused by battery voltage thresholds.
1
CHG_INT1
R
Not applicable
When high, this bit indicates an interrupt caused by a charger mode change.
0
VBUS_INT1
R
Not applicable
When high, this bit indicates an interrupt caused by VBUS voltage threshold.
1
When reading the register, the interrupt bit resets automatically.
Table 71. INTERRUPT_FLAG2 Register, Address 0x35 Bit Descriptions
Bit(s)
Bit Name
Access
Default
Description
7
MR_INT1
R
Not applicable
When high, this bit indicates an interrupt caused by the MR press.
6
WD_INT1
R
Not applicable
When high, this bit indicates an interrupt caused by the watchdog alarm.
5
BUCKPG_INT1
R
Not applicable
When high, this bit indicates an interrupt caused by aVOUT1OK trigger.
4
BUCKBSTPG_INT1
R
Not applicable
When high, this bit indicates an interrupt caused by aVOUT2OK trigger.
[3:0]
Reserved
R
Not applicable
Reserved
.
1
When reading the register, the interrupt bit resets automatically.
Table 72. SHIPMODE Register, Address 0x36 Bit Descriptions
Bit(s) Bit Name
Access Default
Description
[7:1]
Reserved
R
Not applicable
Reserved
.
0
EN_SHIPMODE R/W
0
When high, theADP5360 enters shipment mode. When low, shipment mode is disabled.



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