AD4134 datasheet(71/92 Pages) AD

71 / 92 page

Data Sheet

AD4134

DIAGNOSTICS

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Rev. 0 | 71 of 92

ANALOG INPUT OVERRANGE

An on-chip, full-scale overrange detection monitor flags a bit on

detection of a positive full-scale input voltage between the AINx+

pins and AINx− pins. This detection is enabled on each channel by

using the ERR_OR_AIN_EN bit in the diagnostic control register,

and an overvoltage bit corresponding to the particular channel is set

if the voltage exceeds the full scale corresponding to that channel.

Four overvoltage flags in the AIN_OR_ERROR register correspond-

ing to the four input channels are cleared on a read.

MCLK COUNTER

A stable MCLK is important because the output data rate, filter

settling time, and the filter notch frequencies are dependent on the

master clock. The AD4134 allows the user to monitor the master

clock. When the MCLK_CNT_EN bit in the diagnostic control regis-

ter is set, the MCLK_COUNTER register increments by one every

12,000 master clock cycles. The user can monitor this register

over a fixed period by running a timer in the controller, and the

master clock frequency can be determined from the result in the

MCLK_COUNTER register.

MCLK = Register Data × 12,000/Timer Value

where Register Data is in decimal format.

For example, if MCLK is 24 MHz and the timer is set to 100 ms,

the expected MCLK_COUNTER value is 0xC8. This register wraps

around after it reaches its maximum value.

SPI MONITORING

The AD4134 supports a number of diagnostic measures to improve

the robustness of its SPI.

Accessing Undefined Register Address

When the user tries to access an undefined register address, the

device ignores the instruction and flags an error in the ERR_

SPI_READ bit or the ERR_SPI_WRITE bit. These bits are cleared

on a read.

SCLK Counter

The AD4134 uses an SCLK counter to count the number of

SCLK cycles supplied in each of the read and write transactions

framed by the signal. The device flags an error in the ERR_SPI_

SCLK_CNT bit if the number of SCLK cycles at the end of each SPI

transaction is not an integer multiple of 8. This bit is cleared on a

read. The SCLK counter is not available in minimum I/O mode.

SPI CRC

When the ERR_SPI_CRC_EN bit in the diagnostic control register

is set, a CRC check for all SPI read and write operations is

enabled. The ERR_SPI_CRC bit in the SPI error register is set if

the CRC check fails. This bit is cleared on a read.

For CRC checksum calculations, the polynomial used is x8 + x2 +

x+ 1 and has a reset seed of 0xA5.

The 8-bit checksum is appended to the end of each read and write

transaction. The checksum calculation for the write transaction is

calculated using the 8-bit command word and data. For a read

transaction, the checksum is calculated using the command word

and the data output.

For write or read operation, the host sends the R/W bit, the address

(eight bits), the data (eight bits), and the 8-bit CRC (on R/W,

address, and data).

In a write operation, while the host is sending the CRC on the

SDI line, the slave simultaneously transmits the CRC calculated on

the write + address + data that the slave has received. The slave

executes a write operation only when the received CRC sent by

the host matches with its calculated CRC. The slave sends a 1-bit

status followed by 15 zeros and the 8-bit CRC (see Figure 124).

Figure 124. SPI Write with CRC

In a read operation, while the host is sending the CRC on the

SDI line, the slave simultaneously transmits the CRC calculated on

the command and the read data. The slave sends a 1-bit status

followed by seven zeros, 8-bit read data, and 8-bit CRC (see Figure

125).

The 1-bit status sent by the slave is the error bit, which indicates

that the previous frame had a read, write, or CRC error.

Figure 125. SPI Read with CRC

MEMORY MAP INTEGRITY CHECK

When the ERR_MM_CRC_EN bit is set in the diagnostic control

write access is calculated and the results are stored in memory.

The device then continuously performs the CRC calculation at a

frequency of 2.4 kHz, and compares each output with the CRC

value stored in memory. The device sets the ERR_MM_CRC bit if

the two values are different. This bit is cleared on a read. The CRC

value stored in the memory is also recalculated after each SPI write

transaction.

This feature is useful for detecting a soft error in the memory map.

ODR INPUT FREQUENCY CHECK

An ODR input frequency check applies only to device operation in

ASRC slave mode.

AD4134 Datasheet(PDF) 71 Page - Analog Devices

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