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PC8374L Datasheet(PDF) 40 Page - National Semiconductor (TI) |
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PC8374L Datasheet(HTML) 40 Page - National Semiconductor (TI) |
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40 / 239 page  3.0 Device Architecture and Configuration (Continued) www.national.com 40 Revision1.1 Table 10. Standard General Configuration Registers Index Register Name Description 07h Logical Device Number This register selects the current logical device. See Table 9 for valid numbers. All other values are reserved. 10h Memory Mapping Control Enables the memory mapping of the device and configuration registers. 12h Memory Base Address 1 Indicates selected Memory Base address bits 23-16. 13h Memory Base Address 2 Indicates selected Memory Base address bits 31-24. 20h-2Fh PC8374L Configuration PC8374L configuration registers and ID registers. Table 11. Logical Device Activate Register Index Register Name Description 30h Activate Bits 7-1: Reserved Bit 0: Logical device activation control (see Section 3.3 on page 48) 0: Disabled 1: Enabled Table 12. Memory Space Configuration Registers Index Register Name Description 50h Memory Base Descriptor Controls the mapping of a logical device to I/O or to memory when MEMEN bit in MEMMAP register is set to 1 (see Section 3.7.1 on page 52). Bit 0: Logical device mapping control (see Section 3.3 on page 48) 0: Logical device is mapped to I/O space (default) 1: Logical device is mapped to Memory space Bits 7-1: Reserved Table 13. I/O Space Configuration Registers Index Register Name Description 60h I/O Port Base Address Bits 15 −8 Descriptor 0 Indicates selected I/O lower limit address bits 15 −8 for I/O Descriptor 0. 61h I/O Port Base Address Bits 7 −0 Descriptor 0 Indicates selected I/O lower limit address bits 7 −0 for I/O Descriptor 0. 62h I/O Port Base Address Bits 15 −8 Descriptor 1 Indicates selected I/O lower limit address bits 15 −8 for I/O Descriptor 1. 63h I/O Port Base Address Bits 7 −0 Descriptor 1 Indicates selected I/O lower limit address bits 7 −0 for I/O Descriptor 1. Winbond Electronics Corp. Advanced PC Product Center |
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