PC8374L datasheet(57/239 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

Revision 1.1

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3.7.8

SuperI/O Configuration 4 Register (SIOCF4)

Power Well: VSB3

Location:

Index 24h

Type:

R/W or RO

3.7.9

SuperI/O Configuration 6 Register (SIOCF6)

This register provides a fast way to disable one or more modules without having to access the Activate register of each (see

Section 3.3.1 on page 48).

Power Well: VDD3

Location:

Index 26h

Type:

Varies per bit

Bit

76543

Name

nSWD

Reserved

nPCIRSTO2

Reserved

VddStrap2

Reset

Bit

Description

nSWD (SingleWire Data Multiplex Control). Selects SWD or GPIO.

0: SWD: Health Management (default)

1: GPIOE00

For correct selection of the GPIO on this pin, also see Table 3 on page 18.

Reserved. Must be written with 1 to have GPIO or FANTACH4 functionality on pin 105.

Reserved.

nPCIRSTO2 (PCI Reset Out 2 Multiplex Control). Selects PCIRST_OUT2 or GPIO.

0: PCIRST_OUT2: Glue Functions (default)

1: GPIOE12

For correct selection of the GPIO on this pin, also see Table 3 on page 18.

Note: When using GPIOE12, check that its respective default function ﬁts the system usage of this GPIO. Fail-

ing to do so may result in irreversible damage to the chip.

3-1

Reserved.

VddStrap2. VddStrap2 strap pin Status. Read-Only bit.

The bit holds the sampled VddStrap2 pin value at VDD3 power up.

Bit

Name

LOCKFDS

General-Purpose

Scratch

Reserved

SER1DIS

SER2DIS

PARPDIS

FDCDIS

Reset

Bit

Type

Description

R/W1S LOCKFDS (Lock Fast Disable Configuration). When set to 1, locks itself, SER1DIS, SER2DIS,

PARPDIS and FDCDIS bits in this register and GLOBEN bit in SIOCF1 register by disabling writing to

all of these bits. Once set, this bit can be cleared by Hardware reset.

0: R/W bits are enabled for write (default)

1: All bits (except bits 6-5) are RO

6-5

R/W

General-Purpose Scratch.

Reserved.

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