PC8374L datasheet(75/239 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

Revision 1.1

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3.14.3 GPIO Pin Select Register (GPSEL)

This register selects the GPIO pin (port number and bit number) to be configured (i.e., which register is accessed via the

GPIO pin configuration registers). GPSEL is reset to 00h.

Power Well: VSB3

Location:

Index F0h

Type:

R/W

3.14.4 GPIO Pin Configuration Register 1 (GPCFG1)

This register reflects, for both read and write, the register currently selected by the GPIO Pin Select register. All of the GPIO

pin configuration registers have a common bit structure, as shown below.

Power Well: VSB3

Location:

Index F1h

Type:

Varies per bit

Ports 0 to 1 (With Wake-Up Event Detection Capability)

Bit

76543210

Name

Reserved

PORTSEL

Reserved

PINSEL

Reset

00000000

Bit

Description

Reserved.

6-4

PORTSEL (Port Select). Selects the GPIO port to be configured:

Bits

6 5 4

Mode

0 0 0:

Port 0 (default)

0 0 1:

Port 1

010-111: Reserved

Reserved.

2-0

PINSEL (Pin Select). Selects the GPIO pin of the selected port to be conﬁgured:

Bits

2 1 0

Mode

0 0 0:

Pin 0 (default)

001-111: Binary value of pin numbers 1-7, respectively

Bit

76543210

Name

PDNCTL

EVDBNC

EVPOL

EVTYPE

LOCKCFP

PUPCTL

OUTTYPE

OUTENA

Reset

see Table 31

0000

see Table 31

Bit

Type

Description

R/W or

PDNCTL (Pull-Down Control). Controls the internal pull-down resistor of the selected GPIO pin (see

Section 6.2 on page 111).

0: Disabled (for default value, see Table 31)

1: Enabled (for default value, see Table 31)

Undefined results when both the PDNCTL bit and the PUPCTL bit are set to 1.

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PC8374L Datasheet(PDF) 75 Page - National Semiconductor (TI)

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