PC8374L datasheet(92/239 Pages) NSC

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4.0 System Wake-Up Control (SWC) (Continued)

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Revision1.1

4.3.3

SWC Miscellaneous Control Register (SWC_CTL)

This register contains control and status bits for the SWC module. Its reset value depends on the power well of each bit.

Power Well: Varies per bit

Location:

Offset 01h

Type:

Varies per bit

Bit

43210

Name

LOCKSCF

Reserved

GOOD_

BAT

Reserved

LAST_PWR

_STATE

LED_OPT

Reset

Power Well

VSB3

VBAT

Bit

Type

Description

R/W1S LOCKSCF (Lock SWC Configuration). When set to 1, locks the BLINK and GRN_YLW bits in

SLEDCTL register, and all bits of SWC_CTL, ALEDCTL, LEDBLNK, XLEDCTL, KBDWKCTL, PS2CTL

and PS2KEY0

−7 registers by disabling writing to them (including to the LOCKSCF bit itself). Once set,

this bit can be cleared by Hardware reset.

0: R/W bits are enabled for write (default)

1: All bits are RO

Reserved.

5RO

GOOD_BAT (Battery Good Status). Indicates the status of the VBAT backup power. The bit is

● Reset at any time, if V

BAT <VBATLOW

● Set when either V

DD3 or VSB3 power supply falls below the minimum limit, if VBAT >VBATLOW

When the bit is ‘0’, the value of the LAST_PWR_STATE bit is incorrect and must be ignored.

0: Backup battery low, or not connected (VBAT < VBATLOW)

1: Backup battery good (VBAT > VBATLOW)

4-3

Reserved.

2RO

LAST_PWR_STATE (Last Power State). Samples the value of the SLP_S3 signal when a power

failure occurs. It is powered by the VBAT backup supply, thus preserving its value during a Power Fail

condition (see Section 2.1.2 on page 32). After the AC power returns, reading from this bit returns the

value of the SLP_S3 signal at the time the power failure occurred. The value of this bit must be ignored

when GOOD_BAT bit is 0. Writing to this bit is ignored. At VBAT Power-Up reset, LAST_PWR_STATE

bit is reset to 0.

0: Orderly system shutdown - Main power off by S3 or S5 sleep states (default)

1: Forced system shutdown - Main power off by Mechanical off (G2 state) or by AC power failure

1-0

R/W or

LED_OPT (LED Control Option Select). Selects the Advanced, Standard or Special LED control

option for the two power LEDs (yellow and green).

Bits

1 0

LED Control Option

Advanced:

LEDs controlled by the ALEDCTL and LEDBLNK registers at offsets 02h and

03h,

respectively

Standard:

LEDs controlled by SLEDCTL register at offset 00h

Special:

LEDs controlled by XLEDCTL register at offset 02h (default)

Reserved

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PC8374L Datasheet(PDF) 92 Page - National Semiconductor (TI)

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