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STM8L051F3 Datasheet(PDF) 20 Page - STMicroelectronics |
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STM8L051F3 Datasheet(HTML) 20 Page - STMicroelectronics |
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20 / 96 page  Functional overview STM8L051F3 20/96 DS9178 Rev 4 3.11.1 Window watchdog timer The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. 3.11.2 Independent watchdog timer The independent watchdog peripheral (IWDG) can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the internal LSI RC clock source, and thus stays active even in case of a CPU clock failure. 3.12 Beeper The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz. 3.13 Communication interfaces This section describes the three communication interfaces of STM8L050J3: SPI, I2C and USART. 3.13.1 SPI The serial peripheral interfaces (SPI1) provide half/ full duplex synchronous serial communication with external devices. • Maximum speed: 8 Mbit/s (fSYSCLK/2) both for master and slave • Full duplex synchronous transfers • Simplex synchronous transfers on 2 lines with a possible bidirectional data line • Master or slave operation - selectable by hardware or software • Hardware CRC calculation • Slave/master selection input pin Note: SPI1 can be served by the DMA1 Controller. 3.13.2 I2C The I2C bus interface (I2C1) provides multi-master capability, and controls all I2C bus- specific sequencing, protocol, arbitration and timing. • Master, slave and multi-master capability • Standard mode up to 100 kHz and fast speed modes up to 400 kHz • 7-bit and 10-bit addressing modes • SMBus 2.0 and PMBus support • Hardware CRC calculation Note: I2C1 can be served by the DMA1 Controller. |
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