SPC582BX datasheet(60/115 Pages) STMICROELECTRONICS

60 / 115 page

Electrical characteristics

SPC582Bx

60/115

DS11597 Rev 4

All the Flash operations require the presence of the system clock for internal

synchronization. About 50 synchronization cycles are needed: this means that the timings of

the previous table can be longer if a low frequency system clock is used.

1. Characteristics are valid both for Data Flash and Code Flash, unless specified in the characteristics column.

2. Actual hardware operation times; this does not include software overhead.

3. Typical program and erase times assume nominal supply values and operation at 25 °C.

4. Typical End of Life program and erase times represent the median performance and assume nominal supply values.

Typical End of Life program and erase values may be used for throughput calculations. These values are characteristic, but

not tested.

5. Lifetime maximum program & erase times apply across the voltages and temperatures and occur after the specified

number of program/erase cycles. These maximum values are characterized but not tested or guaranteed.

6. Initial factory condition: < 100 program/erase cycles, 25 °C typical junction temperature and nominal (± 5%) supply

voltages.

7. Initial maximum “All temp” program and erase times provide guidance for time-out limits used in the factory and apply for

less than or equal to 100 program or erase cycles, –40 °C < TJ < 150 °C junction temperature and nominal (± 5%) supply

voltages.

8. Rate computed based on 128 KB sectors.

9. Only code sectors, not including EEPROM.

10. Time between suspend resume and next suspend. Value stated actually represents Min value specification.

11. Timings guaranteed by design.

12. AIC is done using system clock, thus all timing is dependent on system frequency and number of wait states. Timing in the

table is calculated at max frequency.

Table 33. Flash memory Life Specification

Symbol

Characteristics(1) (2)

1. Program and erase cycles supported across specified temperature specifications.

2. It is recommended that the application enables the core cache memory.

Value

Unit

Min

Typ

NCER16K 16 KB CODE Flash endurance

—

100

— Kcycles

NCER32K 32 KB CODE Flash endurance

—

100

— Kcycles

NCER64K 64 KB CODE Flash endurance

—

100

— Kcycles

NCER128K 128 KB CODE Flash endurance

—

100

— Kcycles

NCER256K

128 KB CODE Flash endurance

—

100

— Kcycles

128 KB CODE Flash endurance(3)

3. 10K cycles on 4-128 KB blocks is not intended for production. Reduced reliability and degraded erase time

are possible.

—

100

— Kcycles

NDER16K 16 KB DATA EEPROM Flash endurance

250

—

— Kcycles

tDR1k

Minimum data retention Blocks with 0 - 1,000 P/E

cycles

—

Years

tDR10k

Minimum data retention Blocks with 1,001 - 10,000

P/E cycles

—

Years

tDR100k

Minimum data retention Blocks with 10,001 - 100,000

P/E cycles

—

Years

tDR250k

Minimum data retention Blocks with 100,001 -

250,000 P/E cycles

—

Years

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