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SPC582BX Datasheet(PDF) 23 Page - STMicroelectronics

Part # SPC582BX
Description  SPC58 2B Line - 32 bit Power Architecture automotive MCU Single core 80Mhz, 1MByte Flash, ASIL-B
PDF  115 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPC582BX Datasheet(HTML) 23 Page - STMicroelectronics

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DS11597 Rev 4
23/115
SPC582Bx
Electrical characteristics
23
2. The leakage considered is the sum of core logic and RAM memories. The contribution of analog modules is not considered,
and they are computed in the dynamic IDD_LV and IDD_HV parameters.
3. IDD_LKG (leakage current) and IDD_LV (dynamic current) are reported as separate parameters, to give an indication of the
consumption contributors. The tests used in validation, characterization and production are verifying that the total
consumption (leakage+dynamic) is lower or equal to the sum of the maximum values provided (IDD_LKG +IDD_LV). The two
parameters, measured separately, may exceed the maximum reported for each, depending on the operative conditions and
the software profile used.
4. Use case: 1 x e200Z2 @80 MHz, all IPs clock enabled, Flash access with prefetch disabled, Flash consumption includes
parallel read and program/erase, 1xSARADC in continuous conversion, DMA continuously triggered by ADC conversion, 4
DSPI / 3 CAN / 2 LINFlex transmitting, RTC and STM running, 1xEMIOS running (12 channels in OPWMT mode), FIRC,
SIRC, FXOSC, PLL0-1 running. The switching activity estimated for dynamic consumption does not include I/O toggling,
which is highly dependent on the application. Details of the software configuration are separately. The total device
consumption is IDD_LV + IDD_HV + IDD_LKG for the selected temperature.
5. Gateway use case: One core running at 80 MHz, DMA, PLL, FLASH read only 25%, 7xCAN, 1xSARADC.
6. Flash in Low Power. Sysclk at 80 MHz, PLL0_PHI at 80 MHz, XTAL at 8 MHz, FIRC 16 MHz ON, RCOSC1M off. FlexCAN:
instances: 0, 1, 2, 3, 4, 5, 6 ON (configured but no reception or transmission), ADC ON (continuously converting). All others
IPs clock-gated.
7. Sysclk = RC16 MHz, RC16 MHz ON, RC1 MHz ON, PLL OFF. All possible peripherals off and clock gated. Flash in power
down mode.
8. STANDBY mode: device configured for minimum consumption, RC16 MHz off, RC1 MHz on.



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