XM014532A datasheet(16/99 Pages) XMOS

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XU6--TQ8 Datasheet

CORE

xCONNECT Link to another device switch

CORE

xCORE Tile

xCONNECT

switch

Figure 6:

Switch, links

and channel

ends

Oscillator, Clocks, and PLLs

The device executes using a clock that is scaled up by two on-chip PLLs: a core-PLL that

provides a clock for the digital logic, and a secondary fractional-N PLL for application use.

Both PLLs are driven from an oscillator on the XIN and XOUT pins. If you use a crystal,

you must use a

MHz crystal (±

ppm or better). Otherwise you can supply a clock

between 8 and

MHz, with an accuracy governed by your application. Note that the

USB PHY only supports limited frequencies, see Section .

The clock structure of the device is shown in Figure . The main purpose of the core PLL

is to generate the clocks needed for the digital blocks of the device, including the two

processing cores and the switch. The main purpose of the secondary PLL is to provide

an application clock if required.

The frequencies are typical frequencies used when the device operates at 6

MHz. The

MHz reference frequency can be used by software to time software and interfaces.

The core and switch clocks can be clocked down as required to save power, independent

of the reference clock. In very low power modes, both PLLs can be placed in a low-power

mode, and the whole chip executed directly from the oscillator. In this case, the reference

can no longer operate at

MHz. The labels list the registers in appendices B, C, and D,

that are used to control the clocks.

Core PLL

The core PLL creates a high-speed clock that is used for the switch, tile, and reference

clock. The initial PLL multiplication value is shown in Figure 8:

XM014532A Datasheet(PDF) 16 Page - Xmos Ltd.