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XM014532A Datasheet(PDF) 71 Page - Xmos Ltd. |
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XM014532A Datasheet(HTML) 71 Page - Xmos Ltd. |
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71 / 99 page  XU6--TQ8 Datasheet Bits Perm Init Description Identier RW If set to , the secondary PLL is used as a source for the MIPI PHY clock divider. By default, the output of the core PLL is used. SS_MIPI_CFG_CLK_FROM_APP_PLL : RO - Reserved 6 RW MIPI PHY clock divider disable. When set to , the divider is enabled. SS_MIPI_CFG_CLK_DIV_DISABLE : RW MIPI PHY clock divider. When set to X, the input clock will be divided by 2(X + 1). SS_MIPI_CFG_CLK_DIV x: MIPI PHY clock cong D. Debug source GLOBAL_DEBUG_SOURCE 0x1F Contains the source of the most recent debug event. Bits Perm Init Description Identier : RO - Reserved RW Reserved. GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG : RO - Reserved RW If set, XCore is the source of last GlobalDebug event. GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG RW If set, XCore is the source of last GlobalDebug event. GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG xF: Debug source D. Link status, direction, and network SLINK 0x20 .. 0x28 These registers contain status information for low level debugging (read-only), the net- work number that each link belongs to, and the direction that each link is part of. The registers control links ... |
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