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XM014532A Datasheet(PDF) 46 Page - Xmos Ltd. |
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XM014532A Datasheet(HTML) 46 Page - Xmos Ltd. |
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46 / 99 page  XU6--TQ8 Datasheet Number Perm Description Register identier x8 .. x8 DRW Resources breakpoint mask DBG_RWATCH_ADDR1 x .. x DRW Resources breakpoint value DBG_RWATCH_ADDR2 xC .. xF DRW Resources breakpoint control register DBG_RWATCH_CTRL Figure : Summary (continued) B. RAM base address RAM_BASE 0x00 This register contains the base address of the RAM. It is initialized to x8. Bits Perm Init Description Identier : RW Most signicant 6 bits of all addresses. WORD_ADDRESS_BITS : RO - Reserved x: RAM base address B. Vector base address VECTOR_BASE 0x01 Base address of event vectors in each resource. On an interrupt or event, the 6 most sig- nicant bits of the destination address are provided by this register; the least signicant 6 bits come from the event vector. Bits Perm Init Description Identier : RW The event and interrupt vectors. VECTOR_BASE 8: RO - Reserved x: Vector base address B. xCORE Tile control XCORE_CTRL0 0x02 Register to control features in the xCORE tile Bits Perm Init Description Identier : RO - Reserved : RW Specify size of a connected LPDDR device (options are: 8,6,Mbits, Gbit), XCORE_CTRL0_EXTMEM_DEVICE_SIZE RW Disable RAMs to save power (contents will be lost) XCORE_CTRL0_RAMSHUTDOWN RW Enable memory auto-sleep feature XCORE_CTRL0_MEMSLEEP_ENABLE 8 RW Enable MIPI interface periph ports XCORE_CTRL0_MIPI_ENABLE : RO - Reserved RW Enable the clock divider. This divides the output of the PLL to facilitate one of the low power modes. XCORE_CTRL0_CLK_DIVIDER_EN : RO - Reserved RW Enable External memory interface XCORE_CTRL0_EXTMEM_ENABLE x: xCORE Tile control |
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