XM014532A datasheet(21/99 Pages) XMOS

21 / 99 page

XU6--TQ8 Datasheet

-bit program size s in words.

Program consisting of s × 4 bytes.

-bit CRC, or the value xDABE to indicate that no CRC check should be per-

formed.

The program size and CRC are stored least signicant byte rst. The program is loaded

into the lowest memory address of RAM, and the program is started from that address.

The CRC is calculated over the byte stream represented by the program size and the

program itself. The polynomial used is xEDB88

(IEEE 8.); the CRC register is

initialized with xFFFFFFFF and the residue is inverted to produce the CRC.

Boot from QSPI ash

If set to boot from QSPI ash, the processor enables the six pins specied in Figure ,

and drives the SPI clock. A Quad I/O READ command (xEB) is issued with three address

bytes (x) and one dummy byte. Boot data is then expected from the ash and input

into the device. The clock polarity and phase are / . The ash is assumed to be ready

within

us after power-up, if the ash takes longer than

us the chip should be held

in reset using RST_N until the ash is ready. The ash is assumed to be in its power-up

state, where QSPI-mode accesses will succeed. In particular, the ash device must be

set into quad mode or similar. If the ash is set to an alternate mode, for example QPI,

and the xCORE device is reset, then the subsequent boot will fail.

Signal

Description

Slave Select

SPIO

Data

SPIO

Data

XD6

SPIO

Data

SPIO

Data

SCLK

Clock

Figure

QSPI pins

The xCORE Tile expects each byte to be transferred with the least-signicant nibble rst.

Programmers who write bytes into an QSPI interface using the most signicant nibble

rst may have to reverse the nibbles in each byte of the image stored in the QSPI device.

The pins used for QSPI boot are hardcoded in the boot ROM and cannot be changed. If

required, a QSPI boot program can be burned into OTP that uses different pins.

The boot sequence up to the start of the QSPI boot is outlined in Figure 6

Boot from SPI ash

If set to boot from SPI master, the processor enables the four pins specied in Figure ,

and drives the SPI clock. A READ command (x) is issued with three address bytes

(x), no dummy, then the data is expected from the ash. The clock polarity and phase

are / .

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