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XM014532A Datasheet(PDF) 56 Page - Xmos Ltd.

Part # XM014532A
Description  XCore xcore.ai Microcontroller IC 32-Bit 16-Core 2400MIPs 8KB (8K x 8) OTP 128-TQFP (14x14)
PDF  99 Pages
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Manufacturer  XMOS [Xmos Ltd.]
Direct Link  https://www.xmos.ai/
Logo XMOS - Xmos Ltd.

XM014532A Datasheet(HTML) 56 Page - Xmos Ltd.

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XU6--TQ8 Datasheet
Bits
Perm
Init
Description
Identier
:
CRO
Processor ID of this XCore.
DEVICE_ID0_PID
:6
CRO
Number of the node in which this XCore is located.
DEVICE_ID0_NODE
:8
CRO
XCore revision.
DEVICE_ID0_REVISION
:
CRO
XCore version.
DEVICE_ID0_VERSION
x:
Device
identication
C.
xCORE Tile description
DEVICE_ID1 0x01
This register describes the number of logical cores, synchronisers, locks and channel
ends available on this xCORE tile.
Bits
Perm
Init
Description
Identier
:
CRO
Number of channel ends.
DEVICE_ID1_NUM_CHANENDS
:6
CRO
Number of the locks.
DEVICE_ID1_NUM_LOCKS
:8
CRO
Number of synchronisers.
DEVICE_ID1_NUM_SYNCS
:
RO
-
Reserved
x:
xCORE Tile
description
C.
xCORE Tile description
DEVICE_ID2 0x02
This register describes the number of timers and clock blocks available on this xCORE
tile.
Bits
Perm
Init
Description
Identier
:6
RO
-
Reserved
:8
CRO
Number of clock blocks.
DEVICE_ID2_NUM_CLKBLKS
:
CRO
Number of timers.
DEVICE_ID2_NUM_TIMERS
x:
xCORE Tile
description
C.
PSwitch permissions
DBG_CTRL 0x04
This register can be used to control whether the debug registers (marked with permission
CRW) are accessible through the tile conguration registers. When this bit is set, write
-access to those registers is disabled, preventing debugging of the xCORE tile over the
interconnect.



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