XM014532A datasheet(26/99 Pages) XMOS

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XU6--TQ8 Datasheet

Feature

Bit

Description

Disable JTAG

Set to to disable the JTAG interface to the tile. This makes it

impossible for the tile state or memory content to be accessed

via the JTAG interface.

Disable JTAG to PLL

Set to to disable JTAG access to the PLL conguration register.

Secure Boot

Set to to force the xCORE Tile to boot from address of the OTP

Unied mode

Set to to create one unied OTP rather than two half OTPs for

each tile. This disables registers x-x, and enables reg-

ister x.

Write disable

Disable programming.

Reserved

Set to

Figure

Security

features

USB PHY

The USB PHY provides High-Speed and Full-Speed, device, host, and on-the-go function-

ality. The PHY is congured through a set of peripheral registers (Appendix D.6-D.8),

and data is communicated through ports on the digital node. A library, XUD, is provided

to implement the MAC layer and full USB-device functionality.

The USB PHY is connected to the ports on Tile and Tile as shown in Figure

. En-

abling the USB PHY on a tile will connect the ports shown to the USB PHY. These ports

will not be available for GPIO on that tile. All other IO pins and ports are unaffected. The

USB PHY should not be enabled on both tiles. Two clock blocks can be used to clock the

USB ports. One clock block for the TXDATA path, and one clock block for the RXDATA

path. Details on how to connect those ports are documented in an application note on

USB for xcore.ai.

PORT_1J

PORT_1I

PORT_8B

CLKBLK

RXD

PORT_1H

CLKBLK

PORT_1K

PORT_8A

TXD

xCORE

USB

connector

ID connection is optional

DM may be marked as DN

USB_VDD18

USB_VD D33

3V3 1V8

Regulators

GND

PORT_1E

FLAG0

PORT_1F

FLAG1

USB

PHY

RXD[0..7]

RXRDY

CLK

TXD[0..7]

TXRDY OUT

TXRDY IN

VBUS

1-10uF

USB_DP

USB_DM

LINESTATE0

RXACTIVE

LINESTATE1

RXERROR

SWITCH

USB_SHIM_CFG

USB_ID

Figure

Bus powered

USB-device

USB VBUS

If you use the USB PHY to design a self-powered USB-device, then the device must be

able detect the presence of VBus on the USB connector (so the device can disconnect

its pull-up resistors from D+/D- to ensure the device does not have any voltage on the

D+/D- pins when VBus is not present, “USB Back Voltage Test”). This requires a GPIO pin

XM014532A Datasheet(PDF) 26 Page - Xmos Ltd.

XM014532A Datasheet(HTML) 26 Page - Xmos Ltd.

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