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XM014532A Datasheet(PDF) 66 Page - Xmos Ltd. |
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XM014532A Datasheet(HTML) 66 Page - Xmos Ltd. |
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66 / 99 page ![]() XU6--TQ8 Datasheet D.6 System switch clock divider CLK_DIVIDER 0x07 Sets the ratio of the PLL clock and the switch clock. Bits Perm Init Description Identier :6 RO - Reserved : RW SSwitch clock divider SS_CLK_DIVIDER_CLK_DIV x: System switch clock divider D. Reference clock REF_CLK_DIVIDER 0x08 Sets the ratio of the PLL clock and the reference clock used by the node. Bits Perm Init Description Identier :6 RO - Reserved : RW Software reference clock divider SS_SSWITCH_REF_CLK_DIV x8: Reference clock D.8 System JTAG device ID register JTAG_DEVICE_ID 0x09 Bits Perm Init Description Identier :8 RO SS_JTAG_DEVICE_ID_VERSION : RO SS_JTAG_DEVICE_ID_PART_NUM : RO SS_JTAG_DEVICE_ID_MANU_ID RO SS_JTAG_DEVICE_ID_CONST_VAL x: System JTAG device ID register D. System USERCODE register JTAG_USERCODE 0x0A Bits Perm Init Description Identier :8 RO JTAG USERCODE value programmed into OTP SR SS_JTAG_USERCODE_OTP : RO metal xable ID code SS_JTAG_USERCODE_MASKID xA: System USERCODE register D. LPDDR clock DDR_CLK_DIVIDER 0x0B Sets the ratio of the PLL/APP PLL clock and the LPDDR clock. There is a divide by permanently after the clock divider to create a matched mark space ratio. The LPDDR clock needs to be set to be twice the frequency required. 6 |
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