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XM014532A Datasheet(PDF) 81 Page - Xmos Ltd. |
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XM014532A Datasheet(HTML) 81 Page - Xmos Ltd. |
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81 / 99 page  XU6--TQ8 Datasheet D.6 LPDDR Arbiter RW priority data LPDDR_RW_COMMAND_QUEUE_PRIORITY 0xC009 Bits Perm Init Description Identier :6 RO - Reserved : RW Priority for RW queue . Zero is lowest priority. LPDDR_RW1_PRI : RW Priority for RW queue . Zero is lowest priority. LPDDR_RW0_PRI xC: LPDDR Arbiter RW priority data D. LPDDR Arbiter timeout data LPDDR_ARBITRATION_TIMEOUT 0xC00A Setting this to a non-zero value guarantees that each queue is served at least every N transactions and prevents starvation. Bits Perm Init Description Identier : RO - Reserved : RW Maximum number of transactions until a queue is served. Set to to disable a timeout LPDDR_TOUT xCA: LPDDR Arbiter timeout data D.8 LPDDR PHY control LPDDR_PHY_CONTROL 0xC01D Bits Perm Init Description Identier : RO - Reserved : RW x PHY Control LPDDR_PHY_CONTROL xCD: LPDDR PHY control D. LPDDR LMR cong LPDDR_LMR_OPCODE 0xC01E Bits Perm Init Description Identier : RO - Reserved : RW x LMR opcode LPDDR_LMR_OPCODE xCE: LPDDR LMR cong D. LPDDR EMR cong LPDDR_EMR_OPCODE 0xC01F Bits Perm Init Description Identier : RO - Reserved : RW x EMR opcode LPDDR_EMR_OPCODE xCF: LPDDR EMR cong 8 |
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