DA9062 datasheet(47/101 Pages) RENESAS

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DA9062

PMIC for Applications Requiring up to 8.5 A

Datasheet

Revision 3.8

15-Feb-2022

CFR0011-120-00

47 of 99

8.8.1

NO-POWER Mode

The NO-POWER mode is initial state when powering up the DA9062 for the first time. When the

system supply rises above a threshold, DA9062 enters RESET mode.

8.8.2

RTC Mode

The RTC mode is a low-power mode with only a minimum set of functions to maintain the system

time. All supplies are disabled. RTC mode is entered either after a software request or when the

backup battery is the only supply. If enabled in register RTC_MODE_PD, the power sequencer

proceeds automatically from the POWERDOWN state to RTC mode. If the system supply is

removed, DA9062 will also enter RTC mode. Supply recovery will trigger an exit from RTC mode

automatically. DA9062 will exit RTC mode when nONKEY is asserted, or an RTC alarm is raised.

GPIOs are not operational in RTC mode. With RTC_EN = 1, the DA9062 automatically enters RTC

mode when a VDD_FAULT condition occurs and RTC_MODE_SD = 1, or when VSYS drops below

VPOR_LOWER.

8.8.3

RESET Mode

In RESET mode, the internal supplies, and LDO1 (if configured as an always-on supply) are enabled.

All other DA9062 supplies are disabled.

DA9062 is in RESET mode whenever a complete application shutdown is required. RESET mode

can be triggered by the user, a host processor, or an internal event.

RESET mode can be triggered by the user:

● from a long press of nONKEY (interruptible by host) defined by register SHUT_DELAY

● by pressing a reset switch that is connected to port nRESETREQ (non-interruptible)

RESET mode can be forced from the host processor (non-interruptible):

● by asserting nRESETREQ (falling edge)

● by writing to register SHUTDOWN

DA9062 error conditions that force RESET mode (non-interruptible) are:

● no WATCHDOG write (WDKICK signal assertion) from the host inside the watchdog time window

(if watchdog was enabled)

● an under-voltage detected on VSYS (VSYS < VDD_FAULT_LOWER)

● an internal junction over-temperature

With the INT_SD_MODE, HOST_SD_MODE and KEY_SD_MODE controls, the shutdown

sequences from internal fault, host or user triggered, are individually configured to either implement

the reverse timing of the power-up sequence or transfer immediately to the RESET mode by skipping

any delay from sequencer or dummy slot timers. For the host to determine the reason for the reset a

FAULT_LOG register stores the root cause (either KEY_RESET or NRESETREQ). The host

processor resets this register by writing asserted bits with 1.

KEY_SD_MODE = 1 triggers a complete power on reset (POR) (instead of entering RESET mode)

after the related keys are pressed extendedly.

If an OTP read is aborted, DA9062 enters RESET mode without an asserted bit inside register

FAULT_LOG.

A shutdown sequence to RESET mode will start with the assertion of the nRESET port. After the

sequencer completes the power-down sequence (sequencer position 0), DA9062 continues to

RESET mode with only the following active circuits: LDOCORE (at reduced output voltage 2.2 V),

control interfaces and GPIOs, BCD counter, band-gap and over-temperature/VSYS comparators. All

regulators, except for LDO1 and the backup battery charger, are automatically disabled to avoid

battery drainage. As described in Section 8.1.3, nRESET is always asserted at the beginning of a

shutdown sequence to RESET mode, and remains asserted when DA9062 is in RESET mode.

DA9062 Datasheet(PDF) 47 Page - Renesas Technology Corp

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