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DA9062 Datasheet(PDF) 84 Page - Renesas Technology Corp |
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DA9062 Datasheet(HTML) 84 Page - Renesas Technology Corp |
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84 / 101 page ![]() DA9062 PMIC for Applications Requiring up to 8.5 A Datasheet Revision 3.8 15-Feb-2022 CFR0011-120-00 84 of 99 © 2022 Renesas Electronics Table 99: ID_28_27 (0x090) Field Bit Type Description GP_FALL4_STEP 7:4 R/W Sequencer step to de-assert GPO3 GP_RISE4_STEP 3:0 R/W Sequencer step to assert GPO3 Table 100: ID_30_29 (0x091) Field Bit Type Description GP_FALL5_STEP 7:4 R/W Sequencer step to de-assert GPO4 GP_RISE5_STEP 3:0 R/W Sequencer step to assert GPO4 Table 101: ID_32_31 (0x092) Field Bit Type Description EN32K_STEP 7:4 R/W Sequencer step to enable GPO and RTC clock WAIT_STEP 3:0 R/W Sequencer step for WAIT register functionality Table 102: SEQ_A (0x095) Field Bit Type Description POWER_END 7:4 R/W End of POWER power domain in the sequencer SYSTEM_END <= POWER_END <= MAX_COUNT must be true. SYSTEM_END 3:0 R/W End of SYSTEM power domain in the sequencer PART_DOWN <= SYSTEM_END <= POWER_END must be true. Table 103: SEQ_B (0x096) Field Bit Type Description PART_DOWN 7:4 R/W Sequencer slot to stop at, when going down into STANDBY state. 1 <= PART_DOWN <= SYSTEM_END must be true. MAX_COUNT 3:0 R/W End of POWER1 power domain in the sequencer POWER_END <= MAX_COUNT must be true. |
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