ZAMC4100 datasheet(34/156 Pages) RENESAS

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ZAMC4100 Datasheet

January 26, 2016

The power-up sequence of the whole system is handled by the SBC chip. When the voltage at the VDDE pin

reaches the power-on-reset level (refer to Table 1.5), the system reset is generated. After power-on-reset, the

power-up timer in the SBC starts counting a time tPWRT needed for stabilizing the oscillators and the other analog

circuitry (see Table 1.17). When the analog circuitry is stable, the SBC enables the MCU power supply and

checks its validity. During the MCU supply validity check, the SBC checks that both supply voltages (BUF1V8 and

REG3V3) needed for the MCU operation are in range.

When the supply is valid, the SBC enables the MCU clock and releases its reset. At this point, the SBC chip

switches to the NORMAL Mode, and the MCU can start executing the initialization firmware, running the

diagnostic checks, and switch to the application routine.

If the MCU supply is not valid, the SBC chip executes a time loop in which the internal supply-valid flags are

continuously checked. If the time tMSC expires and the MCU supply is still not in range, the SBC switches to

SLEEP Mode. Switching to SLEEP Mode in the event of an MCU supply failure guarantees that the system stays

passive with very low current consumption (less than 80µA). The ZAMC4100 can switch back to NORMAL Mode

if a valid LIN wake-up is detected. In this case, the MCU supply is checked again and depending on the result, the

system stays in NORMAL Mode or switches to SLEEP Mode.

The ZAMC4100 start-up timing parameters are specified in Table 1.17. Details regarding the ZAMC4100 SLEEP

Mode are given in section 3.5.2.

3.2.

Clock and Reset Sources of the ZAMC4100

All clocks and resets for ZAMC4100 system are generated in the SBC chip. The clock structure of the ZAMC4100

is shown in Figure 3.2, and the reset structure is shown in Figure 3.3.

3.2.1.

Clock Sources

OSCH is the main clock generator for the SBC and MCU. The output clock from OSCH goes directly to the MCU

at 20MHz and to the divider for the SBC resulting in a 4MHz SBC clock.

In SLEEP Mode, the MUX sets the SBC clock to the125kHz OSCL clock. The main purpose of this clock in

SLEEP Mode is to drive the LIN wake-up detection. Also the OSCL clock is used continuously by the WDT.

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