ZAMC4100 datasheet(56/156 Pages) RENESAS

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ZAMC4100 Datasheet

January 26, 2016

Figure 3.10 SPI Frames

CMD

MISO

A) Data WRITE Frame

B) Data READ Frame

C) Command Byte Structure

Legend:

MOSI

WR DATA

SSB

PTR DATA

CMD

MISO

MOSI

SSB

Address[4:0]

R/W

D) Slave Status Byte Structure

7 6 5 4 3 2 1 0

CSN

RD DATA

Reserved bits (keep at 0)

R/W

= Read / not Write

B= Burst read enable

ACCSIG

LINIF

SEIF

ECMCLIF

HSOCIF

HBOCIF

ADCCMPIF

ADCRDYIF

3.7.2.

SPI Write Access

In order to write data in the SBC registers, the MCU should send a WRITE frame as shown in Figure 3.10-A.

There are two bytes that the MCU master should send to SBC:

1. Command byte (CMD) with the R/

W bit = 0, 5-bit address value and bit B = 0.

2. Data byte with the binary value that is going to be written into the corresponding address

When the data is shifted into the SBC, it shifts out the following bytes:

3. Slave status byte.

4. The value of the register pointed to by the SPIDPTR register (for more details, see Table 3.50). By

default, SPIDPTR points to the SBC interrupt status register (IRQSTAT).

Note: Because the burst mode is not allowed during an SPI write, the B bit value is “don’t care.” Keep this value

as ‘0’ for future product compatibility.

In order to have a successful data write, the SPI frame length should be exactly 2 bytes, i.e., 16 clocks. If the SPI

slave receives more than 16 clocks between the falling and rising CSN edges, the WRITE frame is ignored and

no WRITE command is executed.

ZAMC4100 Datasheet(PDF) 56 Page - Renesas Technology Corp

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