ADP3186

Rev. A | Page 7 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VID3

VID2

VID1

FBRTN

CROWBAR

VID0

VID4

PWM1

PWM2

PWM3

SW2

SW1

PWM4

FB

COMP

PWRGD

RAMPADJ

DELAY

EN

SW3

SW4

GND

ILIMIT

RT

CSREF

CSSUM

CSCOMP

VCC

ADP3186

TOP VIEW

(Not to Scale)

Figure 5. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1 to 5

VID4 to VID0

Voltage Identification DAC Inputs. These five pins are pulled up to an internal reference, providing a Logic 1, if

left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.8 V to

1.55 V (see Table 4). Leaving all the VID pins open results in the ADP3186 going into No CPU mode, shutting off

its PWM outputs and pulling the PWRGD output low.

6

CROWBAR

Crowbar Output. This logic-level output can be used to control an external device to short the 12 V supply to

ground to protect the CPU from overvoltage, if CSREF exceeds 2.1 V.

7

FBRTN

Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.

8

FB

Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this

pin and the output voltage sets the no-load offset point.

9

COMP

Error Amplifier Output and Compensation Point.

10

PWRGD

Power Good Output. Open-drain output that signals when the output voltage is outside the proper operating

range.

11

EN

Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.

12

DELAY

Soft Start Delay and Current Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected

between this pin and GND sets the soft start ramp-up time and the overcurrent latch-off delay time.

13

RT

Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator

frequency of the device.

14

RAMPADJ

PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal

PWM ramp.

15

ILIMIT

Current Limit Setpoint/Enable Output. An external resistor from this pin to GND sets the current limit threshold

of the converter. This pin is actively pulled low when the ADP3186 EN input is low, or when VCC is below its UVLO

threshold, to signal to the driver IC that the driver high-side and low-side outputs should go low.

16

CSREF

Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense

amplifier and the power good and crowbar functions. This pin should be connected to the common point of the

output inductors.

17

CSSUM

Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor

currents together to measure the total output current.

18

CSCOMP

Current Sense Compensation Point. A resistor and a capacitor from this pin to CSSUM determine the slope of the

load line and the positioning loop response time.

19

GND

Ground. All internal biasing and the logic output signals of the device are referenced to this ground.

20 to 23

SW4 to SW1

Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases

should be left open.

24 to 27

PWM4 to

PMW1

Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the

ADP3110A. Connecting the PWM3 and/or PWM4 outputs to GND causes that phase to turn off, allowing the

ADP3186 to operate as a 2-, 3-, or 4-phase controller.

28

VCC

Supply Voltage for the Device.