ADP3186 datasheet(12/24 Pages) AD

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ADP3186

Rev. A | Page 12 of 24

Table 4. VID Codes for the ADP3186

VID4

VID3

VID2

VID1

VID0

Output

No CPU

0.800 V

0.825 V

0.850 V

0.875 V

0.900 V

0.925 V

0.950 V

0.975 V

1.000 V

1.025 V

1.050 V

1.075 V

1.100 V

1.125 V

1.150 V

1.175 V

1.200 V

1.225 V

1.250 V

1.275 V

1.300 V

1.325 V

1.350 V

1.375 V

1.400 V

1.425 V

1.450 V

1.475 V

1.500 V

1.525 V

1.550 V

POWER GOOD MONITORING

The power good comparator monitors the output voltage via the

CSREF pin. The PWRGD pin is an open-drain output whose

high level (when connected to a pull-up resistor) indicates that

the output voltage is within the nominal limits specified in the

specifications in Table 4 based on the VID voltage setting.

PWRGD goes low if the output voltage is outside this specified

range, if all the VID DAC inputs are high, or whenever the EN

pin is pulled low. PWRGD is blanked during a VID OTF event

for a period of 100 μs to prevent false signals during the time

the output is changing.

OUTPUT CROWBAR

As part of the protection for the load and output components of

the supply, the PWM outputs are driven low (turning on the

low-side MOSFETs) and the CROWBAR logic output goes high

when the output voltage exceeds the upper crowbar threshold.

This crowbar action stops once the output voltage falls below the

release threshold of approximately 400 mV.

Turning on the low-side MOSFETs pulls down the output as the

reverse current builds up in the inductors. If the output over-

voltage is due to a short in the high-side MOSFET, this action

current-limits the input supply or blows its fuse, protecting the

microprocessor from destruction.

The CROWBAR output can be used to signal an external input

crowbar or other protection circuit.

OUTPUT ENABLE AND UVLO

For the ADP3186 to begin switching, the input supply (VCC) to

the controller must be higher than the UVLO threshold, and

the EN pin must be higher than its logic threshold. If UVLO is

less than the threshold or the EN pin is a logic low, the ADP3186

is disabled. This holds the PWM outputs at ground, shorts the

DELAY capacitor to ground, and holds the ILIMIT pin at ground.

In the application circuit, the ILIMIT pin should be connected

to the OD pins of the ADP3110A. The ILIMIT being grounded

disables the drivers such that both DRVH and DRVL are

grounded. This feature is important in preventing the discharge

of the output capacitors when the controller is shut off. If the

driver outputs were not disabled, a negative voltage could be

generated during output due to the high current discharge of

the output capacitors through the inductors.

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