ADP3186 datasheet(19/24 Pages) AD

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ADP3186

Rev. A | Page 19 of 24

kΩ

0.2

(19)

In this example, choosing a peak current limit of 100 A for ILIM

results in RLIM = 284 kΩ, for which 280 kΩ is chosen as the

nearest 1% value.

The per-phase current limit described in the Current Limit,

Short-Circuit, and Latch-Off Protection section is determined

where:

()

MAX

BIAS

MAX

COMP

PHLIM

−

≅

(23)

AR is the internal ramp amplifier gain.

AD is the current balancing amplifier gain.

RDS is the total low-side MOSFET on resistance.

CR is the internal ramp capacitor value.

The closest standard 1% resistor value is 332 kΩ.

The internal ramp voltage magnitude can be calculated by using

()

kHz

330

0.1

0.2

−

VID

(20)

For the ADP3186, the maximum COMP voltage (VCOMP(MAX)) is

3.3 V, the COMP pin bias voltage (VBIAS) is 1.2 V, and the

current balancing amplifier gain (AD) is 5. Using VR of 560 mV

and RDS(MAX) of 4.8 mΩ (low-side on resistance at 150°C), one

finds a per-phase peak current limit of 61 A. Although this

number may seem high, this current level can be reached only

with an absolute short at the output, and the current limit latch-

off function shuts down the regulator before overheating can

occur.

This limit can be adjusted by changing the ramp voltage (VR),

but make sure not to set the per-phase limit lower than the

average per-phase current (ILIM/n).

The size of the internal ramp can be made larger or smaller. If it

is made larger, stability and transient response improve, but

thermal balance degrades. Likewise, if the ramp is made

smaller, thermal balance improves at the sacrifice of transient

response and stability. The factor of three in the denominator of

Equation 19 sets a ramp size that gives an optimal balance for

good stability, transient response, and thermal balance.

The per-phase initial duty cycle limit is determined by

()

BIAS

MAX

COMP

MAX

−

(24)

In this example, the maximum duty cycle is 0.47.

FEEDBACK LOOP COMPENSATION DESIGN

COMP PIN RAMP

A ramp signal on the COMP pin is due to the droop voltage and

output voltage ramps. This ramp amplitude adds to the internal

ramp to produce the following overall ramp signal at the PWM

input:

()

⎟

⎠

⎞

⎜

⎝

⎛

−

(21)

Optimized compensation of the ADP3186 allows the best

possible response of the regulator’s output to a load change. The

basis for determining the optimum compensation is to make

the regulator and output decoupling appear as an output

impedance that is entirely resistive over the widest possible

frequency range, including dc, and equal to the droop resis-

tances (RO and ROD). With the resistive output impedance, the

output voltage droops in proportion to the load current at any

load current slew rate. This ensures optimal positioning and

helps to minimize the output decoupling.

In this example, the overall ramp signal is 560 mV.

CURRENT LIMIT SETPOINT

To select the current limit setpoint, first find the resistor value

for RLIM. The current limit threshold for the ADP3186 is set

with a 3 V source (VLIM) across RLIM with a gain of 10.4 mV/μA

(ALIM). RLIM can be found using

LIM

(22)

With the multimode feedback structure of the ADP3186, the

feedback compensation must be set so that the converter’s

output impedance works in parallel with the output decoupling

to meet this goal. Several poles and zeros created by the output

inductor and decoupling capacitors (output filter) need to be

compensated for.

A type-three compensator on the voltage feedback is adequate

for proper compensation of the output filter. Equations 25 to 29

are intended to yield an optimal starting point for the design;

some adjustments might be necessary to account for PCB and

component parasitic effects.

For values of RLIM greater than 500 kΩ, the current limit might

be lower than expected, so some adjustment of RLIM might be

needed. Here, ILIM is the average current limit for the output of the

supply.

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