ADP3186 datasheet(17/24 Pages) AD

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ADP3186

Rev. A | Page 17 of 24

The offset is set by a constant current source flowing into of the

FB pin (IFB) and flowing through RB. The value of R

can be

found using Equation

VID

ONL

−

μA

−

(11)

The closest standard 1% resistor value is 2 kΩ.

COUT SELECTION

The required output decoupling for the regulator is typically

recommended by AMD for various processors and platforms.

One can also use some simple design guidelines to determine

what is required. These guidelines are based on having both

bulk and ceramic capacitors in the system.

First select the total amount of ceramic capacitance. This is

based on the number and type of capacitor to be used. The best

location for ceramics is inside the socket. Others can be placed

along the outer edge of the socket as well.

Combined ceramic values of 30 μF to 100 μF are recommended,

usually made up of multiple 10 μF or 22 μF capacitors. Select the

number of ceramics and find the total ceramic capacitance (CZ).

Next, there is an upper limit imposed on the total amount of

bulk capacitance (CX) when one considers the VID on-the-fly

voltage stepping of the output (voltage step VV in time tV with

error of VERR). A lower limit is based on meeting the capacitance

for load release for a given maximum load step ∆IO and a maxi-

mum allowable overshoot. The total amount of load release

voltage is given as ΔVO = ΔIO × ROD.

()

⎟

⎠

⎞

⎜

⎝

⎛

−

≥

VID

MIN

(12)

() ≤

MAX

VID

nKR

−

⎟

⎠

⎞

⎜

⎝

⎛

−

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

(13)

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

ERR

where

To meet the conditions of these expressions and transient

response, the ESR of the bulk capacitor bank (RX) should be less

than or equal to the dynamic droop resistance (ROD). If the

CX(MIN) is larger than CX(MAX), the system cannot meet the VID

on-the-fly specification and might require the use of a smaller

inductor or more phases (and might have to increase the

switching frequency to keep the output ripple the same).

This example uses a combination of MLC capacitors (CZ =

80 μF). The VID on-the-fly step change is from 1.5 V to 0.8 V

(making VV = 700 mV) in 100 μs with a setting error of 3%.

Solving for the bulk capacitance yields

()

μF

mΩ

600

⎟

⎠

⎞

⎜

⎝

⎛

−

≤

MIN

()

≤

700

600

MAX

μs

100

−

⎟

⎠

⎞

⎜

⎝

⎛

−

⎟

⎠

⎞

⎜

⎝

⎛

where k = 3.5.

Using eight 820 μF OS-CON capacitors with a typical ESR of

12 mΩ each yields CX = 6.56 mF with an RX = 1.5 mΩ.

One last check should be made to ensure that the ESL of the

bulk capacitors (LX) is low enough to limit the high frequency

ringing during a load change. This is tested using

()

mΩ

μF

≤

(14)

where Q is limited to the square root of 2 to ensure a critically

damped system. In this example, LX is approximately 500 pH for

the eight OS-CON capacitors, which satisfies this limitation. If

the LX of the chosen bulk capacitor bank is too large, the number

of ceramic capacitors might need to be increased, if there is

excessive ringing.

One should note that for this multimode control technique,

all ceramic designs can be used as long as the conditions of

Equations 11, 12, and 13 are satisfied.

POWER MOSFETS

For this example, the N channel power MOSFETs have been

selected for one high-side switch and two low-side switches per

phase. The main selection parameters for the power MOSFETs

are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive

voltage (the supply voltage to the ADP3110A) dictates whether

standard threshold or logic-level threshold MOSFETs must be

used. With VGATE ~10 V, logic-level threshold MOSFETs (VGS(TH)

< 2.5 V) are recommended.

The maximum output current (IO) determines the RDS(ON)

requirement for the low-side (synchronous) MOSFETs. With

the ADP3186, currents are balanced between phases, therefore

the current in each low-side MOSFET is the output current

divided by the total number of MOSFETs (nSF).

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