ADP3186 datasheet(22/24 Pages) AD

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ADP3186

Rev. A | Page 22 of 24

Initial Transient Setting

19. With the dynamic load still set at the maximum step size,

expand the scope time scale to see 2 μs/div to 5 μs/div. The

waveform may have two overshoots and one minor under-

shoot (see Figure 13). Here, VDROOP is the final desired value.

VDROOP

VTRAN1

VTRAN2

Figure 13. Transient Setting Waveform

20. If both overshoots are larger than desired, try making

the following adjustments. Note that, if these adjust-

ments do not change the response, you are limited by

the output decoupling. Check the output response

each time you make a change as well as the switching

nodes to make sure that the response is still stable.

21. Make the ramp resistor larger by 25% (RRAMP).

22. For VTRAN1, increase CB or increase the switching

frequency.

23. For VTRAN2, increase RA and decrease CA by 25%.

24. For load release (see Figure 14), if VTRANREL is larger

than VTRAN1 (see Figure 13), there is not enough output

capacitance. You need more capacitance or you have

to make the inductor values smaller. (If you change

inductors, you need to start the design again using the

spreadsheet and this tuning procedure.)

VDROOP

VTRANREL

Figure 14. Transient Setting Waveform

Because the ADP3186 turns off all the phases (switches inductors

to ground), there is no ripple voltage present during load release.

Therefore, you do not have to add headroom for ripple,

allowing your load release VTRANREL to be larger than VTRAN1 by the

amount of ripple, and still meet specifications.

If VTRAN1 and VTRANREL are less than the desired final droop, this

implies that capacitors can be removed. When removing capaci-

tors, check the output ripple voltage as well to make sure that it

is still within specifications.

LAYOUT AND COMPONENT PLACEMENT

The following guidelines are recommended for optimal

performance of a switching regulator in a PC system.

General Recommendations

For good results, a PCB with at least four layers is recommended.

This provides the needed versatility for control circuitry

interconnections with optimal placement, power planes for

ground, input, and output power, and wide interconnection

traces in the remainder of the power delivery current paths.

Keep in mind that each square unit of 1 oz copper trace

has a resistance of ~0.53 mΩ at room temperature.

Whenever high currents must be routed between PCB layers,

vias should be used liberally to create several parallel current

paths, so that the resistance and inductance introduced by

these current paths is minimized and the via current rating is

not exceeded.

If critical signal lines (including the output voltage sense lines of

the ADP3186) must cross through power circuitry, it is best if a

signal ground plane can be interposed between those signal lines

and the traces of the power circuitry. This serves as a shield to

minimize noise injection into the signals at the expense of

making signal ground a bit noisier.

An analog ground plane should be used around and under the

ADP3186 as a reference for the components associated with the

controller. This plane should be tied to the nearest output

decoupling capacitor ground and should not be tied to any other

power circuitry to prevent power currents from flowing in it.

The components around the ADP3186 should be located close

to the controller with short traces. The most important traces to

keep short and away from other traces are the FB and CSSUM

pins. The output capacitors should be connected as close as

possible to the load (or connector), for example, a micropro-

cessor core, that receives the power. If the load is distributed,

the capacitors should also be distributed and generally be in

proportion to where the load tends to be more dynamic.

Avoid crossing any signal lines over the switching power path

loop, described in the Power Circuitry Recommendations

section.

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