TSB41AB3IPFP datasheet(41/52 Pages) TI

41 / 52 page

TSB41AB3

IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS418I − JUNE 2000 − REVISED DECEMBER 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

transmit (continued)

(e)

(d)

(c)

(b)

(a)

D0–D7

CTL0, CTL1

SYSCLK

Link Controls CTL and D

PHY High-Impedance CTL and D Outputs

Figure 21. Cancelled/Null Packet Transmission

The sequence of events for a cancelled/null packet transmission is as follows:1

Transmit operation initiated. PHY asserts grant on the CTL lines followed by idle to hand over control

of the interface to the link.

Optional idle cycle. The link may assert at most one idle cycle preceding assertion of hold. This idle cycle

is optional; the link is not required to assert idle preceding hold.

Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of idle. These

hold cycle(s) are optional; the link is not required to assert hold preceding idle.

Null transmit termination. The null transmit operation is terminated by the link asserting two cycles of

idle on the CTL lines and then releasing the interface and returning control to the PHY. Note that the

link may assert idle for a total of three consecutive cycles if it asserts the optional first idle cycle but does

not assert hold. It is recommended that the link assert three cycles of idle to cancel a packet

transmission if no hold cycles are asserted. This ensures that either the link or PHY controls the

interface in all cycles.

After regaining control of the interface, the PHY asserts at least one cycle of idle before any subsequent

status transfer, receive operation, or transmit operation.

interface reset and disable

The LLC controls the state of the PHY-LLC interface using the LPS signal. The interface may be placed into a

reset state, a disabled state, or be made to initialize and then return to normal operation. When the interface

is not operational (whether reset, disabled, or in the process of initialization) the PHY cancels any outstanding

bus request or register read request, and ignores any requests made via the LREQ line. Additionally, any status

information generated by the PHY is not queued and does not cause a status transfer upon restoration of the

interface to normal operation.

The LPS signal may be either a level signal or a pulsed signal, depending upon whether the PHY-LLC interface

is a direct connection or is made across an isolation barrier. When an isolation barrier exists between the PHY

and LLC (whether of the TI bus-holder type or Annex J type) the LPS signal must be pulsed. In a direct

connection, the LPS signal may be either a pulsed or a level signal. Timing parameters for the LPS signal are

given in Table 21.

TSB41AB3IPFP Datasheet(PDF) 41 Page - Texas Instruments

TSB41AB3IPFP Datasheet(HTML) 41 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL