PCA9420BS datasheet(16/85 Pages) NXP

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NXP Semiconductors

PCA9420

Power management IC for low-power microcontroller applications

2. During power-down sequence stage

3. During the on-the-fly change of output voltage

8.12.3 Power-up/down sequence and on-the-fly voltage change

Power-up sequence

The device initiates the default power-up sequence in three different conditions.

Condition 1) The device is off with no any power supply (No valid VIN and No battery with 2.7 V or above

attached). In this condition, two signals below are able to start the default power-up sequence.

• A valid VIN supply on VIN pin

• A voltage on ASYS higher than ASYS_UVLO, a 2.8 V typical

Condition 2) The device stays off by enabling SHIPMODE or in SHIP mode with a battery ≥ 2.8 V attached. In

this condition, two signals are able to start the default power-up sequence.

• A valid VIN supply on VIN pin

• A falling edge on ON key over a 200 µs

Condition 3) The device stays off by enabling PWR_DN_EN bit setting to 1 with a battery ≥ 2.8 V attached. In

this condition, only one signal is able to start the default power-up sequence.

• A falling edge on ON key over a 200 µs

Condition 4) The device stays at VIN OVP condition with no any valid supply attached at VBAT. In result, all

enabled power rails have been off. The following condition re-initiates the power-up sequence.

• The VIN goes below its VIN OVP hysteresis (typ 100 mV)

The power-up sequence by ON key=Low over the debounce time is described as shown in Figure 7.

For the power-up sequence, the chip can set the default sequence per the customer requirement at factory

setting (i.e. MTP option), from one of the 64 options. Once the chip enters the power-down stage, the power-

down sequence is implemented as the reverse of the power-up sequence (i.e., first up, last down).

aaa-033080

POWER-UP SEQUENCE

ON Key

Default-On Rails

Position 1

=1ms

SYSRSTn

POWER-OFF STATE

CONTROL BY PROCESSOR

TPWUP_DLY_INTERVAL

(ON Long-Press Timer, 4s,8s,12s or 16s)

tON_LONG_PRESS

90%

TON_DEBOUNCE

=200µs

NOTE: BUCK1, BUCK2, LDO1 and LDO2 can be assigned to any of positions 1 through 4.

Positions 1 through 4 are LDO1, BUCK2, LDO2, and BUCK1.

(NOTE)

=2ms

The ON Key shall be pulled high

to avoid power recycle initiated

by a programmed ON long-Press

timer expired

PWR_DN_EN bit=1

SHIP_EN_x bit=1

Position 4

POWER-DOWN SEQUENCE

TPWDOWN_DLY_INTERVAL

Figure 7. Power-up/down sequence

On-the-fly output voltage change sequence

PCA9420

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.2 — 26 July 2023

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