PCA9420BS datasheet(14/85 Pages) NXP

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NXP Semiconductors

PCA9420

Power management IC for low-power microcontroller applications

This also applies during the power-up/power-down sequence events, i.e., during power- up or power-down

event, the SYSRSTn signal should assert when any of the enabled rail has not reaches the 90 % to 110 % of its

target value. In other words, the SYSRSTn = 0 (low) needs to remain at such state until all enabled rails reach

90 % of the target values.

Once the condition that caused the SYSRSTn signal to go low is removed, then the SYSRSTn should refresh

accordingly.

Meanwhile, during the voltage change on-the-fly, this could be caused by:

1. Mode setting remains the same, but the user chooses to change one or some of the enabled output rail

voltage by programming its output voltage I2C register setting

2. Mode setting changes by setting different values on MODESEL0/MODESEL1 pins or MODE0_I2C/

MODE1_I2C bits, and it causes one or some of the output rail voltage change

In such case, the SYSRSTn signal does NOT assert when any of the enabled voltage rail output voltage is in

the middle of the transition from initial output voltage level to target level.

8.10 SHIP mode

PCA9420 features a “SHIP mode”, in which the chip provides the lowest quiescent consumption. Ship mode is

designed to operate only from VBAT. Ship mode should not be entered when both VIN and VBAT are present.

To enter the SHIP mode, set the bit of SHIP_EN_x (x can be 0, 1, 2 or 3) in each Mode register to 1. Once the

bit is set to 1, the ship mode immediately takes place regardless of any operation under any mode setting. It

means that the SHIP mode has a higher priority over any conditions and operations.

Upon request to enter the ship mode while the device is running in active mode, a power-down sequence

should take place first and then enter the ship mode.

Once the device enters ship mode, all the I2C register

values are reset to their default setting.

To exit ship mode, one of the following conditions must be satisfied:

1. ON pin falling edge (filtered) applied, less than the long-press duration of time

2. A valid VIN attached. For the VIN attached plugin event, depending on

OPERATION_SEL_FROM_SHIPMODE bit setting, there are two possible operations as described below:

a. OPERATION_SEL_FROM_SHIPMODE=0, upon VIN attached, the chip enables the charging process,

as well as start the power-up sequence for LDO1/LDO2/SW1/SW2 per the setting

b. OPERATION_SEL_FROM_SHIPMODE=1, upon VIN attached, the chip enables the charging process,

LDO1/LDO2/SW1/SW2 remains in shutdown mode and the chip enables only the power-up sequence

upon ON pin falling edge signal.

8.11 Watchdog timer

PCA9420 provides an on-chip watchdog timer, the duration of this watchdog can be programmed via I2C

setting.

Upon initial enable, the watchdog timer starts counting. If the watchdog timer expires before reset, an interrupt

signal is issued (WD_TIMER). Depending on the I2C register setting (nEN_CHG_IN_WATCHDOG), the

following action is also taken:

1. nEN_CHG_IN_WATCHDOG = 0: when the watchdog timer expires, the following operations are expected.

• The SYSRSTn signal asserted (high to low)

• Charging is continued based on battery condition

PCA9420

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Product data sheet

Rev. 4.2 — 26 July 2023

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