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PCA9420BS Datasheet(PDF) 32 Page - NXP Semiconductors

Part # PCA9420BS
Description  Power management IC for low-power microcontroller applications
PDF  85 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCA9420BS Datasheet(HTML) 32 Page - NXP Semiconductors

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NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Bit
Symbol
Default value Type
Function
4
RSVD
1
R/W
Reserved bit
3
VOUTSW1 _MASK
1
R/W
VOUTSW1 Voltage Interrupt Mask bit
0: Not Masked
1: Masked
2
VOUTSW2 _MASK
1
R/W
VOUTSW2 Voltage Interrupt Mask bit
0: Not Masked
1: Masked
1
VOUTLDO1 _MASK
1
R/W
VOUTLDO1 Voltage Interrupt Mask bit
0: Not Masked
1: Masked
0
VOUTLDO2_MASK
1
R/W
VOUTLDO2 Voltage Interrupt Mask bit
0: Not Masked
1: Masked
Table 16. Sub_INT2_Mask register bit description...continued
08h register: Reserved
9.5.9 Top level control_0 (TOP_CTL0, address 09h)
This register contains various configuration bits for top level related functions, part 0. This is a READ AND
WRITE register.
Bit
Symbol
Default value Type
Function
7:5
VIN_ILIM_SEL
[2:0]
010
R/W
VIN input current limit selection: (min/typ/max)
000: 74 mA/85 mA/98 mA, (another default setting by MTP)
001: 222 mA/255 mA/293 mA
010: 370 mA/425 mA/489 mA (default setting)
011: 517 mA/595 mA/684 mA
100: 665 mA/765 mA/880 mA
101: 813 mA/935 mA/1075 mA
110: 961 mA/1105 mA/1271 mA
111: Input current limit disabled
Note: VIN_ILIM_SEL [1] is the only bit that is MTP configurable
4
OPERATION_SEL_
FROM_SHIPMODE
0
R/W
Ship mode wakeup configuration setting
0: upon VIN plug in, the chip enables the battery charging
process, AND starts the power-up sequence for LDO1/LDO2/
SW1/SW2 per the setting
1: upon VIN plug in, the chip enables the charging process,
LDO1/LDO2/SW1/SW2 remains in shutdown mode and the chip
enables only the power-up sequence upon ON pin falling edge
Note: This bit is MTP configurable
3
PWR_DN_EN[1]
0
R/W
Power-down Sequence Enable
0: Do not start power-down sequence
1: Start power-down sequence
2
nEN_CHG_IN_
WATCHDOG
0
R/W
Configure operations in a programmed watchdog timer expired
0: When the programmed watchdog timer expires, the following
operations take place.
Table 17. TOP_CNTL0 register bit description
PCA9420
All information provided in this document is subject to legal disclaimers.
© 2023 NXP B.V. All rights reserved.
Product data sheet
Rev. 4.2 — 26 July 2023
32 / 85



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