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PCA9420BS Datasheet(PDF) 46 Page - NXP Semiconductors

Part # PCA9420BS
Description  Power management IC for low-power microcontroller applications
PDF  85 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCA9420BS Datasheet(HTML) 46 Page - NXP Semiconductors

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NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Bit
Symbol
Default value Type
Function
[1-bit MTP to set default value]
5
4
3
2
1
0
SW1_OUT_0
[5:0]
010100
R/W
SW1 output voltage for mode setting 0 (see below).
[Note: The default value for SW1 _OUT_0[5:0] is set at 1.00 V, but
it should be MTP programmable.]
Table 44. MODECFG_0_0 register bit description...continued
000000=0.500 V
001110=0.850 V
011100=1.200 V
000001=0.525 V
001111=0.875 V
011101=1.225 V
000010=0.550 V
010000=0.900 V
011110=1.250 V
000011=0.575 V
010001=0.925 V
011111=1.275 V
000100=0.600 V
010010=0.950 V
100000=1.300 V
000101=0.625 V
010011=0.975 V
100001=1.325 V
000110=0.650 V
010100=1.000 V
(default)
100010=1.350 V
000111=0.675 V
010101=1.025 V
100011=1.375 V
001000=0.700 V
010110=1.050 V
100100=1.400 V
001001=0.725 V
010111=1.075 V
100101=1.425 V
001010=0.750 V
011000=1.100 V
100110=1.450 V
001011=0.775 V
011001=1.125 V
100111=1.475 V
001100=0.800 V
011010=1.150 V
101000=1.500 V
001101=0.825 V
011011=1.175 V
101001 to 111110=1.5 V
111111 = 1.8 V
Table 45. SW1 output voltage for Mode Setting 0
9.5.29 Mode configuration mode setting 0_1 (MODECFG_0_1, address 23h)
This register contains mode setting A, part 1 configuration register. This is a READ AND WRITE register.
Bit
Symbol
Default value Type
Function
7
RSVD
0
R/W
Reserved bit
6
ON_CFG_0
0
R/W
Mode configuration upon falling edge applied on “ON” pin in
Mode Setting 0:
0: upon valid falling edge applied on “ON” pin, the device
switches back to mode 0 setting (if the device is currently
operating in mode 0 setting, then no mode switch)
1: upon valid falling edge applied on “ON” pin, no mode
switch, the device stays in its current mode setting operation
5
SW2_OUT_0_OFFSET
0
R/W
SW2 output voltage offset selection in mode setting 0
Table 46. MODECFG_0_1 register bit description
PCA9420
All information provided in this document is subject to legal disclaimers.
© 2023 NXP B.V. All rights reserved.
Product data sheet
Rev. 4.2 — 26 July 2023
46 / 85



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