PCA9420BS datasheet(27/85 Pages) NXP

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NXP Semiconductors

PCA9420

Power management IC for low-power microcontroller applications

Bit

Symbol

Default value Type

Function

DEV_ID [1]

DEV_ID [0]

DEV_REV [2]

DEV_REV [1]

DEV_REV [0]

Device revision

Table 9. DEV_INFO register bit description...continued

9.5.2 Top level interrupt status (TOP_INT, address 01h)

The top-level interrupt register contains flags indicating various top level interrupt events as indicated below.

An event latches and only its first occurrence triggers the interrupt signal INTB (if it is not being masked).

Reoccurring events do not change the flag's status or trigger an additional interrupt. If multiple interrupt events

happen, its corresponding interrupt bits in the related registers are “triggered”, however, the INTB signal is only

triggered upon the first interrupt event.

The interrupt event reporting on the device is structured in a two-layer configuration. The interrupt events are

grouped as (1) system level; (2) charger block; (3) buck regulator block; (4) LDO block. When any interrupt

event is triggered, based on which mode it falls into, the related bit for that mode in TOP_INT flags “1”. Any of

the related bits in TOP_INT only change back to 0 when all the interrupt events in its affiliated mode have been

cleared.

This is READ Only register.

Bit

Symbol

Default value

Type

Function

RSVD

Reserved bit

RSVD

Reserved bit

RSVD

Reserved bit

RSVD

Reserved bit

SYS_INT

System level interrupt event trigger indication from events reflected on

Sub level interrupt_0 register.

0: no system level interrupt event triggered

1: system level interrupt event triggered

CHG_INT

Linear battery charger block interrupt event trigger indication

0: no linear battery charger block interrupt event triggered

1: linear battery charger block interrupt event triggered

SW_INT

Buck regulator blocks (SW1, SW2) interrupt event trigger indication

0: no interrupt event on SW1 and/or SW2 blocks triggered

1: interrupt event on SW1 and/or SW2 blocks triggered

LDO_INT

LDO block (LDO1, LDO2) interrupt event trigger indication

0: no interrupt event on LDO1 and/or LDO2 blocks triggered

1: interrupt event on LDO1 and/or LDO2 blocks triggered

Table 10. TOP_INT register bit description

PCA9420

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.2 — 26 July 2023

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