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PCA9420BS Datasheet(PDF) 28 Page - NXP Semiconductors |
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PCA9420BS Datasheet(HTML) 28 Page - NXP Semiconductors |
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28 / 85 page ![]() NXP Semiconductors PCA9420 Power management IC for low-power microcontroller applications 9.5.3 Sub level interrupt_0 (SUB_INT0, address 02h) The sub-level interrupt register contains flags indicating the second-tier interrupt event. For this register, it contains system level related interrupt events. Any of the interrupt sources of this register trigger the SYS_INT bit on the TOP_INT register as long as they are unmasked on the Sub_INT0_Mask register. This is WRITE AND CLEAR register. Bit Symbol Default value Type Function 7 RSVD 0 W/C Reserved bit 6 RSVD 0 W/C Reserved bit 5 ON_PUSH_INT 0 W/C ON falling edge longer than 5 ms happened 4 TEMP_ PREWARNING 0 W/C Die temperature pre-warning interrupt 1: die temp ≥ TWARNING 0: die temp < TWARNING. TWARNING threshold is configured by T_ WARNING [1:0] 3 THEM_SHDN 0 W/C Thermal shutdown interrupt 0: thermal shutdown is not triggered 1: die temp ≥ TSHDN (set in THEM_SHDN [2:0], thermal shutdown is triggered 2 ASYS_ PREWARNING 0 W/C ASYS Pre-Warning Voltage Interrupt 0: ASYS voltage does NOT fall below the threshold set in ASYS_ PREWARNING [1:0] 1: ASYS voltage falls below the threshold set in ASYS_PREWARNING [1:0] 1 WD_TIMER 0 W/C Watchdog Timer Expiration Interrupt 0: The watchdog timer expiration has not happened since the last time this bit was cleared. 1: The watchdog timer expiration has happened since the last time this bit was cleared. 0 IN_PWR 0 W/C Input Voltage Interrupt 0: The IN_PWR bit has not changed since the last time this bit was cleared. 1: The IN_PWR bit has changed since the last time this bit was cleared. Table 11. Sub_INT0 register bit description 9.5.4 Sub level interrupt_0 mask (Sub_INT0_Mask, address 03h) This is a READ AND WRITE register. Bit Symbol Default value Type Function 7 RSVD 0 R/W Reserved bit 6 RSVD 0 R/W Reserved bit 5 ON_PUSH_INT_MASK 1 R/W ON Key falling interrupt mask bit 0: Not Masked 1: Masked Table 12. Sub_INT0_Mask bit description PCA9420 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 4.2 — 26 July 2023 28 / 85 |
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