UPD75P4308GS datasheet(52/61 Pages) RENESAS

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µPD75P4308

Data Sheet U10909EJ2V1DS

APPENDIX A. COMPARISON OF

µPD750004, 754304, AND 75P4308 FUNCTIONS

(1/2)

Item

µPD750004

µPD754304

µPD75P4308

Program memory

Mask ROM

One-time PROM

0000H-0FFFH

0000H-1FFFH

(4096

× 8 bits)

(4096

× 8 bits)

(8192

× 8 bits)

Data memory

000H-1FFH

000H-0FFH

(512

× 4 bits)

(256

× 4 bits)

CPU

75XL CPU

Instruction

When main system

• 0.95, 1.91, 3.81, 15.3

µs (@ 4.19 MHz)

execution time

clock is selected

• 0.67, 1.33, 2.67, 10.7

µs (@ 6.0 MHz)

When subsystem

122

µs

No subsystem clock

clock is selected

(@ 32.768 kHz)

I/O ports

CMOS input

8 (connections of on-chip pull-up resistors are software-specifiable: 7)

CMOS I/O

18 (connections of on-chip pull-up resistors are software-specifiable)

N-ch open-drain I/O

8 (on-chip pull-up resistors

4 (on-chip pull-up resistors

4 (No mask option)

(13-V withstand)

are specified by mask option) are specified by mask option)

Total

30 (No port 4 pin)

Timers

4 channels

3 channels

• Basic interval timer/

• Basic interval timer/watchdog timer

watchdog timer

• 8-bit timer/event counter 0 (fx/22 added)

• 8-bit timer/event counter

• 8-bit timer/event counter 1 (TI1, fx/22 added)

• 8-bit timer

(Can be used as a 16-bit timer/event counter)

• Watch timer

Clock output (PCL)

•

Φ, 524, 262, 65.5 kHz

(main system clock: @ 4.19 MHz)

•

Φ, 750, 375, 93.8 kHz

(main system clock: @ 6.0 MHz)

BUZ output

Yes

Serial interface

Can support three modes

Can support two modes

• 3-wire serial I/O mode

• 3-wire serial I/O mode...MSB/LSB-first switchable

...MSB/LSB-first switchable

• 2-wire serial I/O mode

• SBI mode

Watch mode register (WM)

Yes

System clock control register (SCC)

Sub-oscillator control register (SOS)

UPD75P4308GS Datasheet(PDF) 52 Page - Renesas Technology Corp

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