UPD75P4308GS datasheet(20/61 Pages) RENESAS

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µPD75P4308

Data Sheet U10909EJ2V1DS

(2) Operation legend

A: A register; 4-bit accumulator

B: B register

C: C register

D: D register

E: E register

H: H register

L: L register

X: X register

: Register pair (XA); 8-bit accumulator

: Register pair (BC)

: Register pair (DE)

: Register pair (HL)

XA’

: Expansion register pair (XA’)

BC’

: Expansion register pair (BC’)

DE’

: Expansion register pair (DE’)

HL’

: Expansion register pair (HL’)

: Program counter

: Stack pointer

: Carry flag; bit accumulator

PSW

: Program status word

MBE

: Memory bank enable flag

RBE

: Register bank enable flag

PORTn : Port n (n = 0 to 3, 5 to 8)

IME

: Interrupt master enable flag

IPS

: Interrupt priority select register

××× : Interrupt enable flag

RBS

: Register bank select register

MBS

: Memory bank select register

PCC

: Processor clock control register

.: Delimiter for address and bit

(

××): Contents of address ××

××H: Hexadecimal data

UPD75P4308GS Datasheet(PDF) 20 Page - Renesas Technology Corp

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