VSC8541-02 datasheet(27/101 Pages) MICROCHIP

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Functional Descriptions

VMDS-10513 VSC8541-02 Datasheet Revision 4.1

3.8.1

Low Power State

In the low power state, all major digital blocks are powered down. However, the SMI interface (MDC,

MDIO, and MDINT) functionality is provided.

In this state, the PHY monitors the media interface pins for signal energy. The PHY comes out of low

power state and transitions to the normal operating state when signal energy is detected on the media.

This happens when the PHY is connected to an auto-negotiation-capable link partner or another PHY in

enhanced ActiPHY link partner wake-up state

In the absence of signal energy on the media pins, the PHY periodically transitions from low-power state

to link partner wake-up state, based on the programmable sleep timer (register bits 20E1.14:13). The

actual sleep time duration is randomized from –80 ms to 60 ms to avoid two linked PHYs in ActiPHY

mode entering a lock-up state during operation.

3.8.2

Link Partner Wake-Up State

In the link partner wake-up state, the PHY attempts to wake up the link partner. Up to three complete fast

link pulse bursts are sent on alternating pairs A and B of the Cat5 media for a duration based on the

wake-up timer, which is set using register bits 20E1.12:11.

In this state, SMI interface (MDC, MDIO, and MDINT) functionality is provided.

After sending signal energy on the relevant media, the PHY returns to the low power state.

3.8.3

Normal Operating State

In the normal operating state, the PHY establishes a link with a link partner. When the media is

unplugged or the link partner is powered down, the PHY waits for the duration of the programmable link

status time-out timer, which is set using register bit 28.7 and bit 28.2. It then enters the low power state.

3.9

Media Recovered Clock Output

For Synchronous Ethernet applications, VSC8541-02 includes a recovered clock output pin,

RCVRD_CLK, controlled by register 23G. The recovered clock pin is synchronized to the clock of the

active media link.

To enable recovered clock output, set register 23G bit 15 and bit 0 to 1. By default, the recovered clock

output pin is disabled and held low, including when NRESET is asserted. Register 23G also controls the

clock source, the clock frequency (either 25 MHz, 31.25 MHz, or 125 MHz), and squelch conditions.

Note: When EEE is enabled on a link, the use of the recovered clock output is not recommended due to long

holdovers occurring during EEE quiet/refresh cycles.

3.9.1

Clock Output Squelch

Under certain conditions, such as when there is no link present or during auto-negotiation, the PHY

outputs a clock based on the REFCLK pin. To prevent an undesirable clock from appearing on the

recovered clock pins, the VSC8541-02 device squelches, or inhibits, the clock output based on any of the

following criteria:

•

No link is detected (the link status register 1, bit 2 = 0).

•

The link is found to be unstable using the fast link failure detection feature. The FASTLINK-FAIL pin

is asserted high when enabled.

•

The active link is in 10BASE-T or in 1000BASE-T master mode. These modes produce unreliable

recovered clock sources.

•

CLK_SQUELCH_IN is enabled to squelch the clock.

Use register 23G bits 5:4 to configure the clock squelch criteria. This register can also disable the

squelch feature. The CLK_SQUELCH_IN pin controls the squelching of the clock. The recovered clock

output is squelched when the CLK_SQUELCH_IN pin is high. This pin should not be left floating.

3.10

Serial Management Interface

The VSC8541-02 device includes an IEEE 802.3-compliant Serial Management Interface (SMI) that is

affected by use of its MDC and MDIO pins. The SMI provides access to device control and status

VSC8541-02 Datasheet(PDF) 27 Page - Microchip Technology

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