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VSC8541-02 Datasheet(PDF) 61 Page - Microchip Technology

Part # VSC8541-02
Description  Single Port Gigabit Ethernet Copper PHY with GMII/RGMII/MII/RMII Interfaces
PDF  101 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

VSC8541-02 Datasheet(HTML) 61 Page - Microchip Technology

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Registers
VMDS-10513 VSC8541-02 Datasheet Revision 4.1
52
4.4.3
RGMII Control
The following table shows the register settings for the RGMII controls at address 20E2.
11:10
Invert LED polarity
R/W
Sticky bit.
Invert polarity of LED signals. Default is to drive
an active low signal on the LED pins. For more
information, see Extended LED Modes, page 22.
00
9
Reserved
RO
Reserved.
8
Link status
RO
1: Link is up.
0
7
1000BASE-T EEE
enable
RO
1: EEE is enabled for 1000BASE-T.
0
6
100BASE-TX EEE
enable
RO
1: EEE is enabled for 100BASE-TX.
0
5
Enable 1000BASE-T
force mode
R/W
Sticky bit.
1: Enable 1000BASE-T force mode to allow PHY
to link-up in 1000BASE-T mode without forcing
master/slave when register 0, bits 6 and 13 are
set to 2’b10.
0
4
Force transmit LPI1
R/W
Sticky bit.
1: Enable the EPG to transmit LPI on the MDI,
ignore data from the MAC interface.
0: Transmit idles being received from the MAC.
0
3
Inhibit 100BASE-TX
transmit EEE LPI
R/W
Sticky bit.
1: Disable transmission of EEE LPI on transmit
path MDI in 100BASE-TX mode when receiving
LPI from MAC.
0
2
Inhibit 100BASE-TX
receive EEE LPI
R/W
Sticky bit.
1: Disable transmission of EEE LPI on receive
path MAC interface in 100BASE-TX mode when
receiving LPI from the MDI.
0
1
Inhibit 1000BASE-T
transmit EEE LPI
R/W
Sticky bit.
1: Disable transmission of EEE LPI on transmit
path MDI in 1000BASE-T mode when receiving
LPI from MAC.
00
0
Inhibit 1000BASE-T
receive EEE LPI
R/W
Sticky bit.
1: Disable transmission of EEE LPI on receive
path MAC interface in 1000BASE-T mode when
receiving LPI from the MDI.
0
1.
17E2 bits 4:0 are for debugging purposes only, not for operational use.
Table 60 •
RGMII Control, Address 20E2 (0x14)
Bit
Name
Access Description
Default
15
FLF2 enable
R/W
Fast Link Failure 2 indication enable.
0: Disabled.
1: Enabled.
0
14:13
Reserved
RO
Reserved.
Table 59 •
EEE Control, Address 17E2 (0x11) (continued)
Bit
Name
Access Description
Default



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