VSC8541-02 datasheet(69/101 Pages) MICROCHIP

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Registers

VMDS-10513 VSC8541-02 Datasheet Revision 4.1

4.5.5

Enhanced LED Control

signals.

4.6

Clause 45 Registers to Support Energy-Efficient Ethernet

and 802.3bf

This section describes the Clause 45 registers that are required to support energy-efficient Ethernet.

Access to these registers is through the IEEE standard registers 13 and 14 (MMD access control and

MMD data or address registers).

The following table lists the addresses and register names in the Clause 45 register page space. When

the link is down, 0 is the value returned for the x.180x addresses.

4.6.1

PMA/PMD Status 1

The following table shows the bit descriptions for the PMA/PMD Status 1 register.

Table 76 •

Enhanced LED Control, Address 25G (0x19)

Bit

Name

Access Description

Default

15:8 LED pulsing duty cycle

control

R/W

Programmable control for LED pulsing duty cycle when

bit 30.12 is set to 1. Valid settings are between 0 and

198. A setting of 0 corresponds to a 0.5% duty cycle and

198 corresponds to a 99.5% duty cycle. Intermediate

values change the duty cycle in 0.5% increments.

0x00

7:0

Reserved

Reserved.

Table 77 •

Clause 45 Registers Page Space

Address Name

1.1

PMA/PMD status 1

1.1800

PMA/PMD time sync capable

1.1801

PMA/PMD delay Tx max.

1.1803

PMA/PMD delay Tx min.

1.1805

PMA/PMD delay Rx max.

1.1807

PMA/PMD delay Rx min.

3.1

PCS status 1

3.20

EEE capability

3.22

EEE wake error counter

7.60

EEE advertisement

7.61

EEE link partner advertisement

Table 78 •

PMA/PMD Status 1

Bit

Name

Access Description

15:3

Reserved

Reserved.

PMD/PMA receive link status

RO/LL

1: PMA/PMD receive link up.

0: PMA/PMD receive link down.

1:0

Reserved

Reserved.

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