VSC8541-02 datasheet(68/101 Pages) MICROCHIP

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Registers

VMDS-10513 VSC8541-02 Datasheet Revision 4.1

4.5.3

Fast Link Configuration

indication. The following table shows the settings available for the FASTLINK_FAIL pin.

4.5.4

Recovered Clock Control

signal.

Table 74 •

MAC Configuration and Fast Link Register, Address 19G (0x13)

Bit

Name

Access Description

Default

15:4

Reserved

Reserved.

3:0

Fast link failure setting

R/W

0000: Fast link failure pin enabled.

0001–1110: Reserved.

1111: Output disabled.

0000

Table 75 •

Recovered Clock Control, Address 23G (0x17)

Bit

Name

Access Description

Default

Enable RCVRD_CLK

R/W

1: Enable recovered clock output.

0: Disable recovered clock output.

14:11

Reserved

Reserved.

10:8

Clock frequency select R/W

Select output clock frequency.

000: 25 MHz output clock.

001: 125 MHz output clock.

010: 31.25 MHz output clock.

011–111: Reserved.

000

7:6

Reserved

Reserved.

5:4

Clock squelch level

R/W

Select clock squelch level.

00: Automatically squelch clock to low when the link is not up, is

unstable, is up in a mode that does not support the generation

of a recovered clock (1000BASE-T master or 10BASE-T), or is

up in EEE mode (100BASE-TX or 1000BASE-T slave).

01: Same as 00 except that the clock is also generated in

1000BASE-T master and 10BASE-T link-up modes. This mode

also generates a recovered clock output in EEE mode during

reception of LP_IDLE.

10: Squelch only when the link is not up.

11: Disable clock squelch.

Note: A clock from the Cu PHY will be output on the

recovered clock output in this mode when the link

is down.

When the CLK_SQUELCH_IN pin is set high, it squelches the

recovered clocks regardless of bit settings.

Reserved

Reserved.

2:0

Clock selection

R/W

000: Reserved.

001: Copper PHY recovered clock.

010–111: Reserved.

000

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