TSS461C datasheet(24/57 Pages) ATMEL

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TSS461C

4193G–AUTO–12/04

Control and Status

Registers

Line Control Register (0x00)

•

Read/write register.

•

Default value after reset: 0y00

•

reserved: Bit 2, this bit cannot be set by the user; a 0 must always be written to this

bit.

CD[3:0] Clock Divider

They control the VAN Bus rate through a Baud Rate generator according to the follow-

ing formula:

PC Pulsed CodeOne

The TSS461C will transmit and receive data using the pulsed coding mode (i.e optical

or radio link mode). The use of this mode implies communication via the RXD0 input

and the non-functionality of the diagnosis system.

Zero: (Default at Reset). The TSS461C will transmit and receive data using the

Enhanced Manchester code (RXD0, RXD1, RXD2).

IVTX

Invert TXD output.

IVRX

Invert RXD inputs.The user can invert the logical levels used on either the TXD output or

the RXD inputs in order to adapt to different line drivers and receivers.

One: A one on either of these bits will invert the respective signals.

Zero: (Default at Reset). The TSS461C will set TXD to recessive state in Idle mode and

consider the bus free (recessive states on RXD inputs).

Transmit Control Register

(0x01)

•

Read/Write register

•

Default value after reset: 0x02

7654

3210

MR3

MR2

MR1

MR0

VER2

VER1

VER0

TSCLK

XTAL1

------------------

7654

3210

MR3

MR2

MR1

MR0

VER2

VER1

VER0

TSS461C Datasheet(PDF) 24 Page - ATMEL Corporation

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