TSS461C datasheet(25/57 Pages) ATMEL

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TSS461C

4193G–AUTO–12/04

MR[3:0]: Maximum Retries

These bits allow the user to control the amount of retries the circuit will perform if any

errors occurred during transmission.

Table 5. Retries

Note:

Bus contention is not regarded as an error and an infinite number of transmission

attempts will be performed if bus contention occurs continuously.

VER[2:0]: DLC Version After

Reset

•

000: TSS461A & B

•

001: TSS461C and TSS461C

These bits cannot be set by user; 001 must always be written to these bits.

MT: Module Type

The three different module types are supported (see Section “VAN Frame”):

One: The TSS461C is an autonomous module (Rank 0), an synchronous access mod-

ule (Rank 1) or a slave module (Rank 16).

Zero: The TSS461C is an synchronous access module (Rank 1) or a slave module

(Rank 16).

Diagnosis Control Register

(0x02)

•

Read/Write register

•

Default value after reset: 0x00

MR [3:0]

Max Number of Retries

Max Number of Transmits

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

16+

SDC3

SDC2

SDC1

SDC0

ETIP

ESDC

TSS461C Datasheet(PDF) 25 Page - ATMEL Corporation

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