TSS461C datasheet(38/57 Pages) ATMEL

38 / 57 page

TSS461C

4193G–AUTO–12/04

CHRx: Channel Received and

Receive Enable Command

The two low order bits of this register contain the message status. Together

with

the

RNW and RTR bits of the command register (base_address + 0x01), they define the

message type of this channel (seeSection “Messages Types”). As a general rule (see

Section “Abort”), the status bits are only set by the TSS461C, so the user must reset

them to perform a transmission (CHTx) or/and a reception (CHRx). The received and

transmitted bits are only set if the corresponding frame is without errors or if the retry

count has been exceeded.

Identifier Mask Registers

The Identifier Mask registers (base_address + 0x06 and base_address + 0x07) allow

bitwise masking of the comparison between the identifier received and the identifier

specified.

•

Read/Write registers

ID_M [11:0]: Identifier Mask

A value of 1 indicates comparison enabled.

A value of 0 indicates comparison disabled.

7654321

ID_M 3

ID_M 2

ID_M 1

ID_M 0

xxxx

7654321

ID_M 11

ID_M 10

ID_M 9

ID_M 8

ID_M 7

ID_M 6

ID_M 5

ID_M 4

TSS461C Datasheet(PDF) 38 Page - ATMEL Corporation