TMS320C6421 datasheet(104/227 Pages) TI

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TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

3.7.3.11.2 EMIFA Block Pin-By-Pin Multiplexing Summary

This section summarizes the EMIFA Block muxing on a pin-by-pin basis. It provides an alternative view to

pin muxing in the EMIFA Block. It summarizes the EMIFA Block pin muxing by dividing up the EMIFA

Block based on the PINMUX field that controls the pins. To determine the actual EMIFA Major

Configuration Option for the application need, see Section 3.7.3.11.1, EMIFA Block Major Configuration

Choices.

Table 3-38 shows the pin multiplexing control for each pin in the EMIFA Sub-Block 0. These PINMUX0

and PINMUX1 register fields control the multiplexing in this sub-block:

• PINMUX0: AEM, RMII

Table 3-39 shows the pin multiplexing control for each pin in the EMIFA Sub-Block 1. These PINMUX0

• PINMUX0: AEM, CS5SEL, CS4SEL, CS3SEL, RMII

EMIFA Sub-Block 2 is dedicated to EMIFA pins EM_WAIT/(RDY/BSY), EM_OE, and EM_WE. There is no

pin multiplexing in this block. These pins always function as EMIFA control pins.

Table 3-40 shows the pin multiplexing control for each pin in the EMIFA Sub-Block 3. These PINMUX0

and PINMUX1 register fields control the multiplexing in this sub-block:

• PINMUX0: AEM

104

Device Configurations

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